Issue



Low-temperature RTP for source/drain engineering


06/01/2005







Relatively low-temperature rapid thermal processing offers some new alternatives for addressing the critical question of how to reduce source-drain parasitic resistance through ultralow thermal budget approaches. Solid-phase epitaxial regrowth and nickel silicide as a contact material are examined as potential solutions to reduce parasitic resistance with device scaling beyond the 65nm node.

For continued progress in semiconductor device technology, traditional scaling approaches will need to be augmented by major innovations in materials and devices. In recent years, this has led to great interest in the introduction of new materials such as high-k dielectrics together with metal gates, and in concepts such as the creation of strain in the channel, which increases charge-carrier mobility and provides higher drive currents. Mobility improvements reduce the channel resistance and thus increase the relative significance of the parasitic resistances of the source and drain (S/D) regions. Indeed, one recent analysis shows that at the 90nm node, the ratio of the parasitic S/D resistance (RSD) to the channel resistance is ~0.8 [1]. Further scaling and mobility improvement will make RSD the limiting factor on drive current, which suggests that RSD reduction is a critical issue for progress in CMOS.

RSD arises from several factors, but it is especially important to optimize two elements: 1) abrupt, heavily doped ultrashallow junctions (USJ) at the S/D extensions, and 2) silicide contacts with very low contact resistivity [2]. Many techniques are being explored to create USJs with very small junction depths (XJ) and low sheet resistances (RS). Relatively conventional approaches include reduction of the ion implant energy, co-doping, spacer optimization, and rapid thermal processing (RTP) spike anneals [3]. These methods benefit from the strong existing infrastructure of ion implantation and RTP annealing technologies, but they are unlikely to extend beyond the 45nm node. New forms of RTP, such as millisecond annealing with high-power flash lamps, can provide much higher concentrations of electrically active dopants while introducing minimal diffusion and hold great promise for advanced USJ formation [4]. However, they will require significant R&D for transfer into manufacturing.

More exotic methods, such as pulsed laser annealing or RTCVD of heavily boron-doped SiGe films can provide extremely high dopant activation but face formidable process integration issues [5, 6]. Choices of doping and activation approaches are also influenced by new materials, especially high-k gate dielectrics and metal gates. For the conventional CMOS flow, where the gate stack is formed before the S/D doping and activation anneals, thermal stability of the new materials is very important. For low-power CMOS, where these materials may be essential beyond the 45nm node, low-temperature annealing methods, such as solid-phase epitaxial regrowth (SPER) of heavily doped amorphous layers, may be required [7].

RSD is also very strongly influenced by contact resistance at the silicide contact, especially because it rises with the square of the linear scaling factor [2]. For advanced logic devices, NiSi is the key material for contact formation. It has a low resistivity and can be formed on very narrow lines; it also has the benefit of consuming less silicon than CoSi2. Various schemes for NiSi processing have been considered, but a consensus seems to be emerging on a two-stage process in which an initial anneal at ~300°C is followed by etching and a second anneal at ~450°C [8]. The use of SiGe in the S/D allows new opportunities for contact-resistance reduction due to the bandgap reduction combined with the ability to introduce extremely high concentrations of B [5]. This approach has recently been exploited to introduce strain in the channels of 90nm CMOS devices, and further progress with this kind of approach can be expected [1]. The very fast diffusion of Ni in Si means that precise control of the thermal budget is important in NiSi processing. RTP temperature measurement and control technology has evolved to allow reliable, repeatable processing in this low-temperature regime, combined with the traditional advantages of low thermal budget and an ultrahigh-purity gas ambient. This article focuses on the application of low-temperature RTP for forming advanced USJ and NiSi contacts [9].

SPER for USJs

Figure 1 compares XJ/RS from SPER experiments with recently published data from various USJ doping approaches and with ITRS requirements [10]. The limitations of conventional RTP are evident, although several device manufacturers have already indicated that the conventional method will suffice for 65nm-node manufacturing [11, 12]. Nevertheless, the very attractive XJ/RS capability of SPER indicates its potential for advanced device applications. Although the SPER process is well known [13], the main focus has previously been on furnace SPER [14, 15], whereas the combination of SPER and lamp-based annealing technology is fairly recent [7, 16, 17]. For SPER, the RTP temperature is ~600-800°C and the annealing time lies between several seconds and minutes. SPER is based on amorphization of the substrate prior to implantation of the dopant. During annealing the amorphous silicon recrystallizes, proceeding from the underlying “seed” single crystal, and the implanted dopants are activated during the defect-free regrowth of the amorphous layer [18, 19]. Therefore, the dopant activation can be separated from diffusion and the resulting impurity profile abruptness nearly equals that of the as-implanted distribution. Furthermore, the activation of dopants is much greater than their solid solubility at the SPER temperature. For B-doping, maximum active carrier concentrations of 3.5×1020cm-3 can be reached [20], which correspond to the solid solubility of boron in silicon at ~1245°C.

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Figure 1. Sheet resistance (RS) vs. junction depth (XJ) data from literature obtained by various advanced techniques for the shallowest junction formation, compared to Mattson’s best spike anneal and SPER data from B, BF2, and BF3. All data for p-channel S/D extensions are compared to the 2003 ITRS (dashed lines) [1] and 2001 ITRS update’s 2002 requirements (solid lines). Boron (■) = SPER 650°C, 5 sec; BF2 (●), BF3 (▲) = SPER 650°C, 20 sec; BF2 (▼) = spike 1038°C, 0 sec; literature (✳) = UHV-RTCVD Si1-xGex (~50% Ge) [5]; melt-mode laser thermal processing (LTP) (❍) [6]; flash lamp RTP (∆) [4].

Although SPER has previously been an inherent part of implant annealing, it has always been followed by a high-temperature anneal. The high-temperature process anneals the residual damage that would otherwise be left behind after SPER is complete. This damage is mainly slightly beyond the position of the original boundary of the amorphous-to-crystalline silicon interface. If this “end-of-range” damage is not removed, problems can arise from the residual defects. For example, defects within the depletion region of a p-n junction can increase junction leakage current. As devices are scaled, the junction leakage permitted increases significantly, and it has been suggested that an annealing process that uses only the SPER step could be used to produce very shallow, highly activated regions. Its appeal is mainly based on the fact that it relies on conventional implant and annealing equipment. The SPER technique currently appears to be a promising method for achieving XJ and RS values low enough to meet the performance specifications for the 65 and 45nm nodes (Fig. 1).

Figure 2 shows some SIMS profiles of wafers that were processed using the SPER approach in an RTP system in comparison to a spike-annealed profile. For the SPER approach, 500eV, 1.0×1015cm-2 B (Fig. 2a) was implanted into a wafer preamorphized by a 74Ge+, 30keV, 1.0×1015cm-2 implant, which is also shown. The end-of-range defects observed are mainly responsible for deactivation taking place with extended processing times (minutes) at temperatures <700°C, or quite fast at temperatures as high as 800°C. This poses problems for process integration of SPER, because it needs to be the last high-temperature process that the wafer experiences. One scheme involves forming deep S/D regions before the shallow S/D extensions with a disposable sidewall-spacer process [7]. Other process integration issues, including the compatibility with “halo” doping, also have to be considered [21]. It has been shown that junctions formed by SPER can withstand the thermal cycle needed for NiSi formation [17]. Figure 2b shows SIMS profiles of an as-implanted and SPER-processed (650°C, 20 sec) P2LAD BF3 (0.8kV, 1.0× 1015cm-2) implanted wafer that addresses the 2003 ITRS 65nm node. Comparing junction depths from profiles in Fig. 2 at concentrations of 7-9×1018cm-3 with the requirements of the 2003 ITRS at the 45nm node (Fig. 1) shows that most of the current implant techniques do not even provide as-implanted profiles compatible with this technology node.

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Figure 2. SIMS profiles of a) as-implanted wafers (A); and SPER-processed wafers at 650°C, 5 sec (B: 758Ω/sq.) and 1050°C, 0 sec with 250°C/sec spike-annealed (C: 496Ω/sq.) boron distribution (500eV, 1.0×1015cm-2). The 74Ge+, 30keV, 1.0×1015cm-2 as-implanted profile also is shown (D). b) SIMS profiles for P2LAD BF3 (0.8kV, 1.0×1015cm-2) as-implanted wafers (A) and after SPER process at 650°C, 20 sec (B: 876Ω/sq.). The gaseous ambient for all the regrown and annealed samples was 100ppm of oxygen in nitrogen.

NiSi as a contact material

Beyond the 90nm node, the use of CoSi2 contacts becomes problematic because of a clash of the requirements for low interface roughness and for low sheet resistance on narrow lines [8, 22]. These two requirements impose contradictory trends on the process temperature selected for the second-stage RTP anneal, and the processing window for CoSi2 formation vanishes with further scaling. An attractive approach to overcome this obstacle is replacement of Co with Ni. Although there are at least six different phases in the Ni-Si phase diagram that are stable at room temperature, only three of them (Ni2Si, NiSi, and NiSi2) form during isothermal annealing of Ni layers on Si [23]. The low-resistivity (~15-16µΩ-cm) phase is NiSi, which is formed at temperatures of ~350-650°C. At lower temperatures, the Ni2Si phase is predominant, and at higher temperatures, a transformation to NiSi2 takes place. The silicon consumption for the same sheet resistance is 35% less than for CoSi2 due to a lower resistivity compared to CoSi2 (~18µΩ-cm), as well as the fact that NiSi is a monosilicide. Further advantages include better scaling behavior with a decrease in sheet resistance for decreasing gate lengths down to 30nm, lower diode leakage, and lower contact resistance than that for CoSi2 [24]. The lower processing temperature reduces dopant loss and is essential for integration of new processes such as SPER. The relatively poor thermal stability at higher processing temperatures is a major concern, however, and attention has to be turned to the unintentional formation of NiSi2 grains and agglomeration [25].


Figure 3. RTP temperature control for low-temperature nickel silicide formation at 240, 280, 320, 400, and 450°C with a ramp rate of 15K/sec.
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Because Ni is the main diffusing species in the Ni/Si reaction and there is extra Ni available in areas surrounding small features, excessive silicidation of small structures is critical and can lead to problems such as junction leakage. A possible solution is the introduction of a two-step RTP anneal, similar to the cobalt- and titanium-silicide formation process. Again, there is an initial low-temperature (<300°C) step to form Ni2Si (RTP1). After selective etch of unreacted NiSi, there is a second RTP step (RTP2) at temperatures higher than at least 350-400°C. The extreme low temperatures of the RTP1 step pose significant challenges to modern RTP systems and temperature measurement techniques. Figure 3 shows that such problems can be overcome. Typical pyrometer temperature profiles for the Mattson Helios RTP system are shown for process temperatures between 240°C and 450°C. Although hotplate-based systems have sometimes been used in this regime, the intrinsically superior ambient control in cold-wall RTP systems, combined with the flexibility of lamp-based systems in terms of temperature monitoring, ramp-rate control, and multistage recipes make lamp-based RTP very attractive for this application.

Figure 4 shows the dependence of nickel-to-nickel silicide transformation curves on RTP1 temperature for different processes in a two-step RTP annealing technology. A set of p-type prime 200mm Si wafers of (100) orientation and a bulk resistivity of >1Ωcm were sputtered with 10nm of nickel. Prior to sputtering, the wafers experienced a standard wet cleaning and a presputter cleaning at 300W. After RS measurement on the as-sputtered wafers, they were annealed in an RTP system with 30 sec soak anneals at different RTP1 temperatures from 240°C to 800°C in 20K or 50K steps, respectively (Fig. 3). The ramp-up rate was set to 15K/sec and cooling was by free radiation. The process ambient was controlled at 100% nitrogen with oxygen concentrations <1ppm as monitored by a ZrO2/Y2O3 ceramic oxygen sensor. No uniformity optimization was performed and all lamps were set to the same power. RS was remeasured after annealing, and then wafers were selectively etched according to the standard IMEC procedure. RS values of the wafers were measured before and after the second RTP step of 30 sec at 450°C. Wafers annealed at >450°C during RTP1 were not subjected to the RTP2 step. Sheet resistance measurement was performed on a KLA-Tencor RS-100 four-point probe using probe type A with a circular 121-site pattern and 7mm edge exclusion.


Figure 4. Temperature transformation curves for sheet resistance and uniformity of a 10nm nickel layer after the process sequence of a two-step RTP technology, from sputtering to second RTP anneal.
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The transformation process as shown in Fig. 4 can be described as follows: At low temperatures, Ni2Si formation takes place during RTP1, indicated by an increasing RS compared to the as-sputtered Ni layer. With increasing temperature, more of the Ni is converted to Ni2Si during the 30 sec annealing process in a pure nitrogen ambient. At ~280°C, all of the Ni has been converted to Ni2Si as can be seen by comparing the post-etch curve with the post-RTP1 curve. Because the selective etch removes excess nickel, the post-etch RS is higher as long as not all of the Ni has reacted with Si. In a small plateau between 280°C and 300°C, the RS is independent of RTP1 temperature until the transformation of the Ni2Si phase to NiSi starts at temperatures >300°C, as indicated by decreasing RS values after RTP1 and after etching. Above ~360°C, there is an extremely broad process window (in terms of RS) up to 650°C, where formation of the high-resistivity NiSi2 phase starts.

Transformation of the RTP1-annealed and selectively etched nickel silicide layers during RTP2 results in a constant low RS value of ~7Ω/sq. for RTP1 temperatures >280°C. That is, the final RS is independent of RS values after RTP1, provided that all nickel reacted during RTP1. This is also supported by the fact that post-RTP2 uniformity is independent of temperature uniformity during RTP1 and RTP2 for RTP1 temperatures high enough to react all of the nickel. Thus, an optimum process window for the RTP1 annealing should be at ~280-300°C, where temperatures are low enough to avoid excess silicidation in narrow lines, but at the same time are high enough to provide a temperature-insensitive process for uniform nickel silicide formation.

Conclusion

Relatively low-temperature RTP offers new alternatives for addressing the critical question of how to reduce source-drain parasitic resistance through ultralow thermal-budget approaches. Although advanced high-temperature annealing methods, such as millisecond annealing, can reduce thermal budgets, their interaction with new materials, such as high-k dielectrics, poses challenges. Low-temperature methods such as SPER are promising alternatives for some device technologies, provided that residual defects can be handled. Silicide contact formation is also critical, and low-temperature performance of modern RTP systems was illustrated with a two-step RTP NiSi formation process. The ability to control temperatures as low as 240°C enables a robust process window for NiSi formation at ~280-300°C.

Acknowledgments

The authors thank Anne Lauwers, Richard Lindsay, and Caroline Demeuris of IMEC for specifying nickel layers and selective etching, and for helpful discussions; Zsolt Nényei for critical reading of the manuscript and for many suggestions; and the Mattson people who supported them during experiments and manuscript preparation. P2LAD is a trademark of Varian Semiconductor Equipment Associates. Helios is a trademark of Mattson Technology.

References

  1. S.E. Thompson, in Advanced Short-Time Thermal Processing for Si-Based CMOS Devices II, M.C. Öztürk, et al., eds., The Electrochemical Society, Pennington, p. 412, 2004.
  2. C.M. Osburn, I. Kim, S.K. Han, I. De, K.F. Lee, et al., IBM J. Res. Develop. 46(2/3), p. 299, 2002.
  3. J. Hwang, H. Kennel, P. Packan, M. Taylor, M. Liu, et al., Advanced Short-time Thermal Processing for Si-Based CMOS Devices, F. Roozeboom, E. Gusev, L. Chen, M. Öztürk, D. Kwong, et al., eds., The Electrochem. Society, Pennington, p. 35, 2003.
  4. J.C. Gelpey, K. Elliot, D. Camm, S. McCoy, J. Ross, et al., Proc. ECS Symp. on RTP and Other Short-time Processing Technologies III, p. 313, 2002.
  5. M.C. Öztürk, J. Liu, H. Mo, N. Pesovic, IEDM Tech. Dig., p. 957, 2002.
  6. A. Shima, H. Ashihara, T. Mine, Y. Goto, M. Horiuchi, et al., IEDM Tech. Dig., p. 493, 2003.
  7. J.O. Borland, in Proc. Mat. Res. Soc. Symp. 717, paper C1.1.1, 2002.
  8. J.A. Kittl, A. Lauwers, O. Chamirian, M. Van Dal, A. Akheyar, et al., Proc. ECS Symp. on Advanced Short-time Thermal Processing for Si-Based CMOS Devices 2003-14, p. 177.
  9. J. Niess, S. Paul, S. Buschbaum, P. Schmid, W. Lerch, Mat. Sci. and Eng. B 114-115, p. 141, 2004.
  10. International Technology Roadmap for Semiconductors 2003 Edition, http://public.itrs.net/Files/2003ITRS/Home2003.htm.

  1. E. Morifuji, M. Kanda, N. Yanagiya, S. Matsuda, S. Inaba, et al., IEDM Tech. Digest, pp. 655-658, 2002.
  2. B.J. Pawlak, R. Lindsay, R. Surdeanu, X. Pages, W. Vandervorst, et al., Proc. ECS Symp. on Advanced Short-time Thermal Processing for Si-Based CMOS Devices 2003-14, p. 99.
  3. L. Csepregi, J. Gyulai, S.S. Lau, Mat. Chem. and Phys. 46, p. 178, 1996.
  4. K. Tsui, K. Takeuchi, T. Mogami, IEDM Tech. Digest, p. 9, 1999.
  5. H. Shimada, I. Ohshima, S.-I. Nakao, M. Nakagawa, K. Kanemoto, et al., IEDM Tech. Digest, p. 67, 2001.
  6. W. Lerch, S. Paul, D.F. Downey, E.A. Arevalo, Proc. ECS Symp. on Advanced Short-time Thermal Processing for Si-Based CMOS Devices 2003-14, p. 43.
  7. W. Lerch, S. Paul, J. Niess, F. Cristiano, Y. Lamrani, et al., Proc. ECS Symp. on Advanced Short-time Thermal Processing for Si-Based CMOS Devices II 2004-01, p. 89.
  8. B. L. Crowder, J. Electrochem. Soc. 117(6), p. 671, 1970.
  9. B.L. Crowder, J. Electrochem. Soc. 118(6), p. 943, 1971.
  10. E. Landi, S. Guimaraes, S. Solmi, Appl. Phys. A4, p. 135, 1987.

  1. R. Lindsay, B. Pawlak, J. Kittl, K. Henson, C. Torregiani, et al., Proc. Mat. Res. Soc. Symp. 765, paper D7.4.1, 2003.
  2. A. Lauwers, M. de Potter, O. Chamirian, R. Lindsay, C. Demeurisse, et al., Microelectronics Eng. 64, p. 131, 2002.
  3. C. Lavoie, R. Purtell, C. Coia, C. Detavernier, P. Desjardins, et al., Proc. ECS Symp. on RTP & Other Short-time Proc. Technologies III 2002-11, p. 455.
  4. A. Lauwers, J.A. Kittl, A. Akheyar, M. Van Dal, O. Chamirian, et al., Proc. ECS Symp. on Advanced Short-time Thermal Processing for Si-Based CMOS Devices 2003-14, p. 167.
  5. D. Ma, D.Z. Chi, W.D. Wang, A.S.W. Wong, S.J. Chua, Proc. Mat. Res. Soc. Symp. 716, p. 47, 2002.

Juergen Niess is process applications manager at Mattson Thermal Products GmbH, Dornstadt, Germany; ph 49/7348-981-238, fax 49/7348-981-239, e-mail [email protected].

S. Paul is a senior process engineer focused on ultrashallow junction formation at Mattson Thermal Products GmbH.

P. Schmid is a senior process engineer at Mattson Thermal Products GmbH.

W. Lerch is a senior manager, technology, at Mattson Thermal Products GmbH.

Paul Timans is director of technology for the RTP Products Business Unit of Mattson Technology, Fremont, CA.