Using a single-wafer spin system to prevent dielectric film peeling
06/01/2005
The challenges associated with modern wafer processing in semiconductor manufacturing are being driven by an increase in the number of processing steps, increasing complexity of device technologies, process integration flows, and new materials incorporation. An increase in the number and variation of toolsets necessary in high-volume manufacturing also increases the risk of cross-contamination with subsequent loss of yield and device performance. Of particular concern are the wafer backside and bevel edge, which can be sites for contamination due to handling and unintentional processing. A process optimization is presented for bevel edge removal of low-k films using a spin processor to prevent peeling of the film material from the wafer bevel edge during subsequent anneal and deposition steps.
Attention has been given to general cleaning of wafer backsides and bevels [1-3], but information on similar cleans related to specific emerging materials is scarce. Low-k dielectric, carbon, or fluorine-doped films are being integrated into back-end-of-line (BEOL) stacks to improve device performance and allow for device scaling. Successful integration of these films remains challenging [4, 5] and there is a need for considerable process development and optimization, including controlled deposition and cleaning of low-k films across the wafer. These processes inherently require tight control of bevel edge wrap of the low-k film stack to prevent issues in subsequent film deposition and defectivity excursions.
Process flow
Bevel edge film peeling was shown to be a yield issue in LSI Logic’s process flow. A typical backend process sequence is a metal process flow in which a low-k material is deposited as an intermetal dielectric (IMD) between the underlying layers and the cap layer. In IMD formation, low-k material is processed at chemical mechanical polishing (CMP); a pattern is masked, etched (via first), and followed by a plasma ash step. A standard solvent post-etch residue clean step is followed by an anneal step to outgas any remaining moisture prior to metal deposition. At this point, flaking of bevel-wrapped low-k material is most likely to occur. (Edge bead removal [EBR] at via dry etching is not enough for low-k removal due to CVD and CMP characteristics on the wafer edge.) Ti and TiN are deposited as barrier materials, and the via is plugged by a W deposition followed by W-CMP. The last step in the process is Al deposition.
The peeling causes wafer yield fallout that can be addressed by an expensive and costly process scheme that adds another four process steps: photomask, dry etching, ashing, and solvent clean. These steps reduce cycle time and greatly promote the likelihood of increased defectivity. This solution, however, was unacceptable for high-volume manufacturing and another solution was proposed that involved the implementation of a single clean step after the IMD deposition. The SEZ spin processor can place a wafer face down on a N2 cushion, allowing a wafer backside to be processed without the need for frontside protection. The chuck design and chemical dispense control further allow for the chemistry to be wrapped around from the wafer backside to the wafer frontside with a controlled distance and a predefined edge exclusion. Film peeling was observed to only happen in the presence of a low-k film; it is not observed on an edge without a low-k film.
Process optimization
Process condition. Development for the wet-etch process utilized a Taguchi L9 design of experiments (DOE) method that is summarized in Table 1. Target values were set at 0.7 ± 0.3mm edge exclusion, with no pin marks. For this experiment, four variables were chosen for variation: wafer rotation speed (500, 750, and 1000rpm), N2 flow rate (90, 110, and 130L/min), etching time (20, 40, and 60 sec), and wafer shift counts (0, 2, and 4 counts). The wafer shift allows the pins holding the wafer on the chuck to rapidly open and close, thereby letting the wafer rotate while the chuck is braked, eliminating pin marks associated with unetched material. For this experiment, the etchant used was 49% HF at 23ºC and a 1.0L/min flow rate for all runs. Each chemical dispense was followed by a customary DI wafer rinse step and spinning N2-enhanced drying step. A test stack of P-SiO2 (base), low-k, and P-SiO2 (cap) on Si was used as a test vehicle and is referred to as the POR stack. The cleaned edge exclusion area was monitored via optical microscope.
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Factor effects. Figure 1 shows the effects for wet edge etching on the factors used in the Taguchi L9 DOE in Table 1. Based upon our observations, wafer rotation speed appears to have the strongest influence on bevel edge distance for the chosen chemistry. There is a linear relationship between rotation speed and edge exclusion ranging from 0.35-1.2mm. In the wet edge, edge exclusion is inversely proportional to the wafer’s rotation speed, which is consistent with the relative change in centrifugal force involved. As speed is decreased, so is force, which means that the relative amount of time the chemistry stays in contact with the wafer increases. As there is a tendency for chemistry to migrate to the wafer frontside due to surface tension, the relative contact time for chemistry also increases. Thus, the migration will continue for a longer time and move further in toward the wafer center. A similar observation is associated with etching time, but it is much less pronounced relative to the rotation speed. Finally, as expected, the wafer shift and N2 flow rate were shown to be less critical factors influencing the edge exclusion area for the ranges and the chemical investigated. HF flow rate and HF temperature were fixed in this experiment. Thus, their relative effects were not tested.
 Figure 1. Factor effects on wet edge etching. |
Best condition. Figure 2 shows optical microscope images of the edge exclusion at 12 equidistant locations on a wafer edge. The process conditions used are also shown and represent the best observed conditions from the DOE analysis (and are referred to as “best-known methods” or BKM). These corresponded to a uniform edge exclusion of 0.7 ± 0.2mm (the target was 0.7 ± 0.3mm). These conditions were run with and without wafer shift; and wafer shift was found to be necessary for uniform film removal.
 Figure 2. Edge etch pictures at 12 equally spaced positions around wafer edges. |
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Under-layer dependency
Under high-vacuum conditions, a variety of film materials and film thicknesses may be present on the wafer edge, bevel, and backside. Our solution needed to be robust enough to handle these situations and provide a production solution.
Surface condition. We investigated the impact of various surface conditions on the etching of the bevel edge and edge exclusion zones. Figure 3 shows the relationship between surface condition and edge etching of a SiN (CVD) film deposited on all sides of a bare, unpatterned Si wafer. Next, the POR stack was deposited on the frontside and the process BKM developed for the bare Si condition described above was again used. The presence of a SiN underlayer surface visually improves edge exclusion uniformity, but increases the overall edge exclusion distance. This is consistent because SiN surfaces have higher wettability/lower surface tension characteristics than Si due to their relevant relative hydrophobicities. Based upon the explanation above, the chemistry will travel faster across the wafer for a given wafer spin speed, thereby extending further around the wafer and increasing the relative edge exclusion in the same process time.
 Figure 3. Relationship between surface condition (with and without CVD nitride film) and edge etching. |
Step height. To determine the effect of a surface step at the wafer edge on the edge exclusion, a series of experiments were run. Figure 4 shows the relationship between step height and edge exclusion distance for our POR film stack on a bare Si wafer with and without a step, as a function of wafer spin speed.
 Figure 4. Relationship between step height and edge etching. |
This step was formed at the wafer edge on a Si substrate via dry etching. Varying step heights were generated (0µm, 0.5µm, 1.0µm) and the POR test stack was deposited. Again, the edge exclusion target was set at 0.7mm. For these tests, all wet etch steps were held constant using BKM (40 sec; wafer shift, 4 times; and N2 flow, 110L/min) for a 0.7mm exclusion, except for wafer-spin speed time.
 Figure 5. Edge etching a) with and b) without a step. |
The observed results indicate that the edge exclusion is most influenced by increased step height. For the 0µm and 0.5µm cases, there is very little change in the trend of edge-exclusion distance characteristics as a function of step height. However, for the 1.0µm case, there is a distinctive change in the edge exclusion distance. In all cases, the BKM wafer-spin speed condition of 750rpm achieves the desired 0.7mm edge exclusion. However, the effect of the step height is more pronounced as spin speeds are decreased to 450rpm. Figure 5 shows optical microscopy images of edge exclusion zones with and without a 1.0µm step. The images show etching beyond the desired edge exclusion region when no step is present; however, this is not observed in the case where the step is present with wet etching being observed in the desired region.
It is common in manufacturing settings to have an edge step, particularly on an underlying interlayer dielectric (ILD) film. This edge is formed by dry EBR to prevent photoresist flaking. A POR film stack with 0.7mm edge exclusion was deposited on an ILD bulk film that had a 1µm step at the edge. Figure 6 shows SEM cross-section images of the test wafer before wet-etch sample and after wet etching with BKM for 0.7mm edge exclusion. The resultant etch was actually 0.7 ± 0.1mm.
Dry vs. wet
There are two fundamental approaches possible to perform edge etching: dry and wet etch. To compare the efficacy of both techniques, each approach was compared for defectivity, process cost, and cycle time impact. In Table 2, the defect density is compared for dry etch vs. wet etch. We observed a defectivity reduction using wet vs. dry etch, and this improvement contributed to a gain of 5% in wafer sort vs. yield after dry etch. Without the implementation of an EBR and edge exclusion clean, the effective yield was very low, ~20-25%. When the cost of the process implementation for wet vs. dry etch was calculated, the wet etch was found to be 90% less expensive than a comparable dry etch. Last, the wet etch proves to have a considerably lower impact on cycle than dry etch - almost 75%.
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Conclusion
Wafer-edge etching with a defined, uniform edge exclusion was investigated using an SEZ spin processor for the purpose of preventing IMD film flaking and peeling after thermal anneal. For the variable tested, it was shown that wafer rotation speed had the biggest influence in the distance of the edge exclusion zone from the wafer bevel. Furthermore, the distance of the edge exclusion zone can be affected by the presence of an edge step that is present in the underlying film stack. The surface termination of the underlying layer also affects both the edge exclusion distance and the etching uniformity. Implementation of a wet etch using a single-wafer spin processor results in lower process costs, reduced cycle time, and lower defect density, leading to higher yield compared to a conventional dry edge-etching process.
Acknowledgments
The authors would like to thank Jason McNichols and Khaldoun Barakat in LSI Logic’s ILM department for defect analysis; Steve Reder and Greg Piatt in LSI Logic’s equipment engineering department for their assistance in tool setup; and Keith Pemberton at SEZ America Inc. for his support.
References
- M. Miyajima, Semiconductor World, Vol. 17, No.13, 124, 1998.
- T. Hara, K. Sakata, K. Sato, K. Kinoshita, Y. Kouzuki, “Cleaning of Cu by CSE Method,” Extended Abs. of the 59th Autumn Meeting of the Japan Society of Applied Physics, 700, 1998.
- M. Itoh, Y. Ishii, T. Jinbo, H. Akimori, T. Futase, et al., International Symposium on Semiconductor Manufacturing, 149, 1999.
- Y.H. Wang, R. Kumar, J. Electrochem. Soc., 151, 73, 2004.
- S. Thagella, A. K. Sikder, A. Kumar, J. Electrochem. Soc., 151, 205, 2004.
Nobuyoshi Sato is a process engineer at LSI Logic Corp., 23400 NE Glisan, Gresham, OR 97030; ph 503/618-5554, fax 503/618-6580, e-mail: [email protected].
Chris Bowker is the engineering manager for LSI Logic.
Leo Archer is director of emerging technologies at SEZ America.