Gaining synergy with strained silicon
05/01/2005
Strained silicon is one of the key technology boosters identified by the International Technology Roadmap for Semiconductors (ITRS) as being essential to the continuation of classical scaling. The enhanced carrier mobilities made possible through strain engineering result in noteworthy device performance improvements. Current candidates for high-k gate dielectrics cause significant carrier degradation in the channel, and high-mobility channels will be needed to restore the losses. Without strained Si, high-k transistors will have no performance improvement over transistors with conventional gate oxides.
There are several different approaches for introducing strain into the Si channel of deeply scaled MOSFETs. Of these, process-induced (uniaxial) strain and bulk wafer (biaxial) strain are the two most promising candidates, and they are featured in the R&D activities of device manufacturers worldwide. The successful production of 300mm strained silicon-on-insulator (sSOI) wafer samples also has been announced, and sSOI substrates soon will become commercially available for both partially and fully depleted CMOS devices.
Given the diversity of different strained Si materials available, it is not surprising that many IDMs and foundries are evaluating all the options to determine which provide the best solutions in terms of performance, manufacturability, and cost.
Which strained silicon option is best?
So which strained Si options provide the best solutions for both today’s and tomorrow’s technology requirements? Can process-induced strain be scaled without introducing unacceptable levels of process complexity and cost? And is the position of global strain becoming stronger in the future?
The 2004 edition of the ITRS [1] stated that higher “transconductance/mobility improvement factors” will be required for the 65nm technology node. The levels of strain needed to obtain such improvements are currently only achievable using global strain methods, in which the lattice constant is engineered using an epitaxial process. Global strain will also be essential to the manufacture of sSOI substrates.
It is very important that process-induced strain, global strain, and SOI are not considered competing technologies. New sSOI materials are synergistic, and it is highly feasible that process-induced and global strain used in a complementary fashion could provide similar synergy (e.g., nMOS enhancement provided by global strain and pMOS enhancement by process-induced strain).
Global strain
Epitaxial strained Si layers grown on relaxed SiGe buffers provide the highest levels of strain and strain uniformity with a 1% (typical) Si lattice deformation, resulting in a strain value of 1.5GPa.
Although the process integration challenges of building sub-100nm MOSFETs on bulk strained Si wafers are not trivial, many device manufacturers are close to solutions and are now working with strained Si suppliers to identify which substrate parameters are most relevant to performance and yield. One of the recent findings of this interaction is that pMOS carrier mobility enhancement is a strong function of short length-scale microroughness. A significant reduction in strained Si surface microroughness, achieved by optimizing the epitaxy process, results in reported transconductance improvements of up to 28% for short-channel pMOSFETs (Fig. 1).
 Figure 1. Comparative transconductance data for 90nm pMOS devices (70nm physical gate length). |
The good news is that this improvement is possible without the intermediate CMP step typically used to remove the relaxed buffer layer cross-hatch prior to growing the strained Si layer. This means that the complete strained Si wafer can be epitaxially grown in a single pass through the CVD reactor. Reducing the number of process steps translates into significant defect reduction, avoidance of undesirable interfaces, and a degree of crystallinity that can exceed that of a bulk Si substrate due to the high quality of the epitaxial growth.
Significant reduction to both cost and cycle time is achieved by manufacturing strained Si wafers in a single-stage process, which brings the cost of high-quality bulk strained wafers in line with SOI.
The Raman data shown in Fig. 2 demonstrate that strain relaxation of 99% is uniformly maintained across the wafer surface. Strain levels of 1.15 ±0.01GPa are demonstrated for strained Si layers grown on relaxed SiGe buffers with a germanium content of 17%.
 Figure 2. Raman data showing cross-wafer strain uniformity. |
Another important point is that global strain processes currently are the only viable method for producing sSOI substrates. Such materials combine the advantage of enhanced mobility with the low-power benefits of SOI and are needed for manufacturing fully depleted CMOS devices at and beyond the 65nm node. The manufacture of such substrates requires the layer transfer of an epitaxially grown, high-quality strained Si layer onto a thermally oxidized second wafer.
Process-induced strain
The benefits of using process-induced strain already have been successfully demonstrated at the 90nm technology node. This approach allows the device performance of pMOS and nMOS transistors to be tuned independently and avoids introducing threading dislocations into the channel regions.
Options for process-induced strain on ultrathin-body (UTB) SOI and sSOI are limited because the current techniques for imparting compressive strain in the pMOS channel use a deeply recessed, selective SiGe structure. This approach works well for bulk substrates, but the depth of recess required cannot be supported in the very thin layer of Si available on UTB SOI substrates.
Tight control of the individual manufacturing stages employed in process-induced strain is essential to achieving consistent strain levels. Control of parameters including the pMOS spacer recess depth, recess isotropy, and selective SiGe process are additional requirements for current devices. Additional process-induced strain stages will be needed to leverage further performance enhancements. Each of these processes introduces an additional source of variation to the final strain level and adds to product cost and cycle time.
Future convergence
The current ITRS shows that the mobility/transconductance improvement factor will have to increase from 1.4× to 2× when the technology node transitions from 90nm to 65nm in 2007. This improvement factor is necessary to achieve the required saturated drive-current values and is a monumental jump from the current value of 1.3×. No one has yet proposed how we will reach this level of improvement, but strain in one or more forms will be essential.
Epitaxial strained Si layers grown on higher Ge-content buffer layers (Ge >30%) would provide the required level of enhancement for both holes and electrons. The caveat is that it would also mean reduced Si-layer critical thickness, increased dislocation defect density, and increased Ge diffusion into the strained Si.
Layer transfer of such films to produce sSOI with higher levels of strain would be SiGe-free, thus avoiding many of the major integration issues, including Ge diffusion. Another benefit is that any vertical dislocation defects would terminate at the oxide, which reduces potential leakage paths to the substrate. Complete absence of SiGe also resolves arsenic diffusivity issues and plasma etching difficulties, and overcomes additional leakage problems due to the reduced bandgap at the drain electrode.
The process integration challenges are replaced by the substrate manufacturing challenges of producing high-quality strained Si layers and successfully transferring them to produce sSOI.
It is likely that the combined benefits of global strain, SOI, and process-induced strain will be needed to deliver the levels of device performance enhancement required by the 2004 ITRS. Independently, they will not be able to do so.
Reference
- International Technology Roadmap for Semiconductors, 2004 edition, SIA; http://public.itrs.net.
Robert Harper received his BSc (Hons.) from the U. of Wales, Swansea, and is currently studying for an MSc in advanced silicon processing and manufacturing technologies. He is technical sales manager at IQE, Beech House, Cypress Dr., St. Mellons, Cardiff, Wales CF3 OLW; e-mail [email protected].