Material challenges for silicon nanoelectronics
05/01/2005
 Figure 1. A MOS transistor with a 10nm channel length could support the 22nm silicon nanoelectronics generation [2]. The MOS gate size is identified by the arrows. |
IC manufacturing technology entered the era of nanotechnology in 2000, when circuits were produced with a minimum feature size <100nm. The industry introduces a new manufacturing technology every two years with feature sizes reduced by 30%, which increases density 2× with each generation (Moore’s Law) [1]. Chau [2] has shown that transistors for ICs can continue to shrink below 10nm (Fig. 1) and operate effectively, which should support technologies beyond 2011. Many materials, however, will need to be replaced or improved for advanced manufacturing. Nanostructured materials open opportunities for innovation to extend silicon technology and Moore’s Law into the second decade of this century, but significant challenges need to be overcome.
Nanomaterials
The use of nanomaterials in IC manufacturing has differing levels of complexity depending on the application, and this may determine the timeframe for their use. To integrate a new material into an IC is very difficult because it must be compatible with all the materials and processing it contacts. Materials used in processing, such as chemical mechanical polish slurry or photoresist, are less difficult, because they serve a specific function. They make contact only with a limited number of materials, and they are not integrated into the circuit.
Small amounts of nanomaterials, nanoparticles, or macromolecules can be added to polymers to change the electrical or mechanical properties or diffusion of gases though them, so this may have a lower complexity and could be used in package applications. Thus, nanomaterials may be used first for less challenging applications where they significantly improve performance, and research should be done to investigate their integration into more challenging applications.
Challenges to IC manufacturing
Over time, the thickness of the gate dielectric (e.g., SiO2) has been reduced to ~1nm, several molecular layers thick, to increase transistor speed, but at these thicknesses it is a poor electrical insulator and significant current leaks through it. One solution is to replace the SiO2 with a higher dielectric-constant material that can be thicker, yet perform like a thinner SiO2 layer.
Chau [3] reported high-performance transistors based on a high dielectric-constant gate dielectric deposited using a process with atomic level control. This atomic layer deposition (ALD) technology sequentially exposes the wafer surface to a gas that saturates the surface, and then introduces a new gas to react with the surface layer and grow a molecular layer. This new material should deliver higher-performance transistors for several generations.
Researchers are exploring whether silicon nanowires or carbon nanotubes can be used as CMOS devices in future IC technologies. While many researchers have been able to fabricate individual transistors, significant challenges must be overcome to make them useful. For carbon nanotubes or silicon nanowires to replace existing CMOS transistors, we need to be able to grow them in predefined locations, with correct orientation, and have reproducible electronic properties. These materials currently are grown in random locations and orientations with highly variable electronic properties, so much progress is needed for this to be a viable option for sub-10nm technology generations.
As transistor feature sizes are reduced, the size and separation between the electrical interconnects is decreased, the electrical resistance of interconnects increases, and the capacitive coupling between adjacent metal interconnects increases (Fig. 2). To reduce the electrical resistance of interconnects, the industry has changed the metal from aluminum to copper, but one has to encase the copper in a barrier (~20nm thick) to keep it from diffusing into the silicon and damaging the transistors.
To reduce the capacitive coupling between adjacent interconnects, the industry has changed interlevel dielectrics from SiO2 to SiO2 doped with fluorine or carbon to reduce the dielectric constant. While the fluorine and carbon doping decreases the dielectric constant, it also makes this interlevel dielectric mechanically weaker and more brittle, which renders the assembly in a package much more challenging.
In future technologies, the industry will need new lower dielectric-constant materials, and most techniques to reduce the dielectric constant also introduce nanopores into the dielectric. Many are evaluating nanoporous dielectrics self-assembled by organic molecules, but these films often are weak and absorb process chemicals, which are detrimental in subsequent processing and weaken the films. So these self-assembled films must be dramatically improved to be useful, or new chemical vapor deposition techniques and chemical precursors must be developed to produce lower-k dielectrics.
The second major challenge for interconnects is to dramatically reduce the thickness of the barrier layer that encapsulates the copper interconnect. As interconnect feature size is decreased, the ~20nm barrier layer, which has a higher electrical resistance, will become a significant part of the interconnect cross-sectional area and degrade the resistance. A much thinner barrier layer, still effective and also compatible with possibly nanoporous lower-k dielectrics, will be needed. This may require new growth techniques with atomic control of the composition and film thickness.
As the size of interconnects decreases, the industry will still need to planarize the interconnect layers, but the process pressure will need to be reduced. CMP uses particles approaching 100nm and will probably need to use smaller ones or even more radical chemicals to reduce pressure.
Conclusion
Nanomaterials have interesting properties that may be useful in IC technology, but the earliest potential applications would be to modify package-polymer mechanical properties or to be used as additives in chemicals or materials for processing wafers. ALD is being evaluated to deposit high-k gate dielectrics in atomically structured layers; this technique may be used in future IC manufacturing. The potential application of nanomaterials as device elements in sub-10nm IC technologies has many complex challenges, and much work must be done for this to be realized. As the electronics industry explores novel device technologies for potential integration beyond 2015, nanomaterials may provide the basis for fabrication and operation of these devices.
References
- International Technology Roadmap for Semiconductors, 2003 edition, Interconnect section, Semiconductor Industry Association.
- R. Chau, B. Doyle, M. Doczy, S. Datta, S. Hareland, et al., “Silicon Nano-Transistors and Breaking the 10nm Physical Gate Length Barrier,” 61st Device Research Conf., 2003.
- R. Chau, S. Datta, M. Doczy, J. Kavalieros, M. Metz, “Gate Dielectric Scaling for High-Performance CMOS: From SiO2 to High-k,” Intl. Workshop on Gate Insulator 2003.
C. Michael Garner is director of the materials technology operation for Intel, Santa Clara, CA; ph 408/765-2588, e-mail [email protected].