Selete outlines damage-control roadmap for porous low-k
04/01/2005
Selete has developed methodology for reducing chemical and mechanical damage to ultralow-k films. By using low-pressure CMP and dummy patterns in the dielectric, an interconnect module with a dielectric constant of 1.8 was produced.
 Figure 1. Test modules using porous low-k materials with dielectric constants of 1.8 and 1.6 achieved yields >95% on 300mm wafers. (Source: Selete) |
Beyond the 65nm node, semiconductor devices will have to turn to porous dielectrics to reduce k values down to the 2.5-1.6 level. But these ultralow-k materials have correspondingly low strength, as indicated by their low Young’s Modulus values, and will require new approaches to withstand processing.
Low-pressure CMP looks effective in reducing delamination of delicate porous dielectric materials. Reducing CMP pressure from 3.5 to 0.8psi reduced delamination by an order-of-magnitude. We experienced no delamination and 95% yields in sheet resistance from our interconnect test modules that used porous dielectrics with k values of 1.8 and 1.6, with a modulus as low as 1.6GPa. Selete has begun using a process that controls pressure separately in each region of the CMP head for uniform polishing at these low pressures across the 300mm wafer.
Also key to strengthening weak ultralow-k dielectric films is using dummy patterns to prevent stress migration defects. The heat of annealing after copper deposition tends to cause the Cu to penetrate the barrier metal and get into the dielectric when the dielectric constant is <2. Lower annealing temperatures, stronger low-k materials, and better capping films can all help, but the most effective dielectric strengthening was obtained by introducing dummy patterns to divide the wide bars into narrower pillars that better withstood the pressure from expanding Cu. Stress migration defects were sharply reduced as the density of the dummy pattern increased (see Fig. 2 on p. 22).
Chemical damage may become a more serious issue than mechanical damage as chipmakers try to improve the effective k value of the stack in coming generations by eliminating the relatively high-k SiO2 barrier film that now protects the dielectric from contact with contaminating chemicals and slurry, but selecting proper cleaning chemistries can eliminate much of the problem. A low-k dielectric (k = 2.3) was soaked in various CMP cleaning solutions at 30× their usual concentrations for 10 min and measured the change in k value. Though all the cleaning solutions increased the dielectric constant somewhat, some pushed it up by as much as fourfold, while others increased it only slightly, to ~2.5. Less damage to the dielectric will become a new standard for CMP chemistry selection.
The choice of material also can make a big difference in how the low-k dielectric withstands chemical damage when directly subjected to CMP without an intervening barrier layer. Direct CMP raised the k value of the materials tested by widely varying amounts, ranging from 2% to 18%. Annealing restored performance in all cases, but not back to the original values. A CVD SiOC film with k = 2.8 ended up with only a 1.8% reduction in the dielectric constant after direct CMP and annealing. One spun-on porous MSQ of k = 2.3 ended up with a 9.8% increase; but another variant of MSQ with the same k value saw only a 3.2% reduction, to a still respectable k value of 2.35. A test module made with this dielectric without a barrier layer showed normal values for circuit resistance and interlayer capacitance.
Seiichi Kondoh, Selete,
SST partner Nikkei Microdevices