Advanced process technology interconnect integration challenges
04/01/2005
One of the main challenges of 65nm and 45nm Cu/low-k interconnect integration is the development of processes to accommodate low-k dielectrics with k = 2.5-3.0. Key issues include dual-damascene patterning, line resistance, low-k integrity, chemical mechanical planarization (CMP) compatibility, and copper defectivity.
Selecting the right dual-damascene process scheme is critical because it needs to work over a range of technology nodes, and with a variety of low-k dielectric stacks. The chosen scheme also needs a wide patterning window, in terms of via and trench aspect ratios, as well as the ability to use sensitive resist materials. With thinner resists, the proper integration schemes must allow for pattern transfer into hard mask and also isolate the dielectric stack from the resist.
Multiple approaches have been employed, including bilayer hard mask, dual bottom antireflective coating, and trilayer or bilayer resists. Patterning and process limitations encourage the trilayer approach, which is an evolutionary extension of the “via first” method, consisting of a combination of resist and dielectric layers. By using a low-temperature oxide to seal the barrier, which prevents poisoning, thin lithographic films can be deposited on the oxide because it also can be used as a hard mask during the organic barrier open. Although more complicated than schemes used in 130nm and 90nm generations, the trilayer approach adds only one additional deposition step.
Line resistance
At 65nm and below, the narrow metal linewidth exerts more stringent requirements on the barrier metal. To ensure the Cu does not diffuse over time and lead to reliability failures, simply thinning the barrier is not enough. Barrier coverage needs to be more uniform and effective in the high aspect-ratio structures encountered.
One type of physical vapor deposition (PVD) chamber uses a magnetron source that provides a higher metal-ionization fraction to improve barrier step coverage over conventional PVD. The high ionization fraction enables a larger volume of material deposited inside the feature, but with the same deposition thickness on the field. By redistributing the relatively thick material from the via bottom to the sidewall, conformality is improved and asymmetric buildup of barrier material within the via is limited. For the 65nm technology node, we achieved total barrier thicknesses of <120Å. The high step coverage (Fig. 1) and overall film integrity provide good reliability with a much lower effective resistivity (2.3-2.4µΩ-cm).
Alternatively, atomic layer deposition (ALD) barrier metallization most likely will be used for generations beyond 45nm. With its molecular-level controllability, 100% step coverage and smooth surface morphology, ALD is especially promising for minimizing line resistance.
Maintaining low-k integrity
CVD-based SiOC (k ~ 2.5-3.0) films are the industry’s primary choice for low-k materials. They will be widely used to at least the 45nm generation, and likely beyond, due to their extendibility and acceptable mechanical strength that can withstand the forces of CMP as well as packaging techniques. Equally important, this film has been engineered to ensure maximum adhesion and minimum low-k dielectric shift throughout the dual-damascene process by careful control of each interface surface.
The etch stop layer (ESL) also is important to integration. To maintain overall lower effective k value, SiC with a dielectric constant of ~4.5 must replace the conventional SiN (k = 7). The SiC ESL needs to be thin (<400Å), yet offer a significantly lower k value than SiN. Adhesion of the SiC film to copper is critical in enhancing electromigration performance [1]. Using a process featuring in situ removal of CuO followed by SiC deposition improves interface control. Even with the potential introduction of electroless copper capping, SiC films likely will continue to be used for etch control.
Additional integration challenges include minimizing or eliminating sidewall damage during resist strip and plasma damage during etch to maintain the effective k value throughout the stack.
CMP compatibility
 Figure 2. Improvements in the uniform removal with Ecmp compared to conventional CMP on different structures: a) 0.12µm, b) 0.48µm, and c) 2.0µm. |
Low-k materials have lower mechanical strength than SiO2 or fluorosilicate glass, posing problems for CMP. SiO2-based oxides have a hardness of ~8GPa compared to ~2GPa for the low-k SiOC material. Thus, using a level of down force appropriate to conventional CMP to polish low-k materials, and also barrier layers, frequently will cause peeling or delamination from the previous layers.
One technique - electrochemical mechanical polishing (Ecmp) - utilizes electric charge through an electrolyte chemical for the bulk Cu removal step, where the most vigorous shear stress is typically applied. With virtually no down force - just enough pressure (0.3psi) to maintain contact between pad and wafer - shear is removed from the process regime. This has two benefits: enabling compatibility with future, more porous low-k materials; and reducing the dishing that is inherent to a high down-force CMP process. (The data presented is for a film hard enough to polish with high down force; however, the benefit even for these harder films is much better planarity, which affects parametrics.) Figure 2 shows significantly improved planarity achieved with Ecmp vs. a conventional process on a film with k~2.9. In all the results shown for planarizing 0.12µm, 0.48µm, and 2.0µm structures, Ecmp improved removal uniformity for higher planarity performance compared to conventional CMP.
Copper defectivity
Micropits and missing Cu are defects frequently observed after CMP. A novel technique is employed to characterize pit density. By using top-down SEM images, grain boundary and pit size densities can be quantified. Using a SEM defect review tool and grain boundary density imaging, one can optimize seed-layer sidewall overhang, electrochemical plating (ECP) gap fill, in situ anneal, and queue time between barrier/seed to ECP and ECP to CMP to minimize pit defects in Cu lines.
In small geometries with increasing aspect ratios, greatly improved control of ECP plating chemistry is required to achieve void-free gap fill and minimize defects, including much tighter control of additive concentration and usage rate, as well as limiting byproduct buildup in the plating bath.
Conclusion
New approaches and technologies that break through 65nm and 45nm-node integration challenges have been developed. Because of the cost and complexity of the technologies, partnerships between equipment companies and chip manufacturers are essential to rapidly identify solutions and turn these into cost-effective processes that can be used in volume manufacturing.
Reference
- D. Padhi, G. Dixit, “Key Process Parameters for Copper Electromigration,” Solid State Technology, Vol. 46, No. 11, Nov. 2003.
Michael Armacost received his BA in chemistry from Western Maryland College and his MS in chemical engineering from Clarkson U. He is senior director of the Applied Materials Maydan Technology Center Integration Group, 3050 Bowers Ave., Santa Clara, CA, 95054; e-mail [email protected]. John T.C. Lee, Applied Materials Inc., Santa Clara, California