3D packaging issues for ultrasmall systems-in-a-cube
04/01/2005
The intriguing concept of ultrasmall, autonomous, intelligent computing devices for wireless sensor networks could open up a wide range of applications, from human-health monitoring to highly distributed tiny systems for safety and environmental data collection. To get there, the industry must develop and deploy new 3D systems-in-package (SiP) technologies, including ultrathin-chip stacking processes and methods for inclusion of MEMS sensors and power sources. This article explores techniques and challenges in creating a new class of intelligent systems-in-a-cube (SiC) assemblies for autonomous networking devices.
In the field of SiP, the main focus of the industry today is die stacking and wire bonding of multiple chips in a single package. Such multichip packages may be realized using the existing technologies and require limited but product-specific development. Nevertheless, due to wire-bonding techniques, this approach is generally restricted to simple-die and memory-die stacking, which require few or very ordered interconnects between the stacked die.
 3D Stack module for a wireless body area network. The module can combine computing, wireless communication, sensing, and power scavenging. (Photo courtesy of IMEC) |
There is, however, a more flexible approach: Rather than stacking bare die, each die is packaged individually, using chip-scale packaging (CSP) technology, and then stacked afterward to build 3D systems-in-a-cube. These SiC assemblies have several advantages. The number of interconnects between the different layers can be significantly reduced because each layer is designed as a well defined subcircuit block, integrating the die and its associated components (such as passives). Another advantage is the possibility to test the different subsystems before final assembly into the SiP, avoiding any issues with yield loss due to the known good die (KGD) problem. What’s more, each building-block CSP can be manufactured independently in a standard process flow, making it cost-effective.
To create 3D SiP structures, different approaches are gaining popularity in the industry, but not all exploit the advantages cited, and interconnects often are the bottleneck. Wire-bonded 3D SiPs are similar to die stacks, but instead of tiling dies together, individual subsystems are mounted. The benefits are, as explained previously, a low number of interconnects between the layers, high yield, and low cost. Because wire bonding is used, however, this approach will always have limitations on well ordered interconnects. Folded 3D packages are basically 2D flexible interconnects, folded in the third dimension. This approach reduces space requirements, but leaves most other problems untouched. Because all components are assembled on one linear carrier, although flexible, it limits - rather than increases - the design freedom. Thus, the advantages of working with individual subsystems cannot be fully exploited. In a third alternative, the SiC structure uses interconnect routing paths on the sidewalls of the cube. With only a single interconnect layer employed, no “cross-over” of lines is allowed, which results in a more complex interconnect design. Apart from other limitations, this approach does not resolve any KGD issues because all layers are integrated (e.g., molded) in one cubic package, instead of being individual components.
 Figure 1. Example of 3D SiP system for a Bluetooth wireless module, which is made with two stacked chip-scale packages. |
Using a novel technique, IMEC researchers have created a high-density 3D stack (Fig. 1), which integrates RF, digital electronics, and a decoupling layer [1]. A similar stack concept was initially used to support development of a wireless electroencephalogram SiC module of 1cm3 to monitor brain activity, but it also can integrate a variety of body sensors and other functions for additional applications. This 3D package differs from existing alternatives in that it fully exploits the advantages of 3D stacking. The stacking of individually tested subsystems avoids the KGD problem and, moreover, no wire-bonding process is used. The first-level interconnects (between chip and carrier) are created with flip-chip bonding using thermocompression mounting. Before mounting on carriers, chips are bumped using a stud-ball bumping process suitable for fine-pitch IC applications. Solder balls assure interconnection between the different layers in a cube (see phot on p. S3). The stacking in the z direction and the final mounting of the SiP are compatible with existing SMT and BGA assembly processes, improving the 3D SiC’s chances for commercialization and large-scale production.
Chip stacking
With the techniques described, it is now possible to achieve 3D systems that fit into 1cm3. To reduce stack heights to the order of 1mm, stacking of individual chips in the SiC is inevitable. New techniques need to be developed, employing ultrathin wafers and interconnections that avoid the limitations of wire bonding when stacking die.
To limit the stack height, chips must be thinned to ≤100µm before they are diced from wafers. Device performance should not be affected by the necessary thinning steps. Thinned wafers can present problems in handling and processing [2]; they become flexible (Fig. 2), so temporary carriers are needed in ultrathin-chip stacking. Thinning itself is done mostly by grinding, CMP, and polishing processes. In some cases, even reactive ion etching can be used.
 Figure 2. A thinned wafer becomes flexible. |
In addition to thinning, “through the wafer interconnections” (vias) are required to fully exploit the possibilities of 3D integration. Several choices must be made on the types of vias being used, depending on the specific requirements of the system and process steps. The first factor is when vias are formed in the manufacturing process flow. If the interconnect vias are made on the wafer before circuits are built, then typically poly-Si is used as a filling material. But if vias are made as part of the back-end-of-line process steps, then copper is a more likely choice for filling. The choice of filling material also is determined by the temperature budget; both approaches have their advantages.
Second, the size of vias determines how they are constructed. Through-wafer interconnect vias could range from 100-150µm (to connect modules in different chip layers) down to 1µm (to connect individual dies in 3D stacks using extremely high-density vias, such as layering memory atop logic chips). For low-density applications, the required aspect ratio (via depth over via size) is quite relaxed (~1:1), and benzocyclobutene (BCB) or parylene can be used as an isolating layer. However, completely filling such a via with conductive material (Cu) is difficult [3]. A sufficiently flowing polymer - for example, BCB - can fill any remaining voids after conductive layer deposition. Several concepts can achieve this. Two are shown in Fig. 3. In high-density via applications, high aspect ratios are needed (up to 50:1) where filling is also an issue: The rate of deposition at the bottom of the vias is slower than at the top, raising the risk of small voids.
 Figure 3. Two concepts for filling remaining voids after the conductive layer. |
Finally, bumping-feature sizes for interconnects between chips become a factor. For larger bump sizes, relatively known techniques can be used, such as Au- or Al-ball bonding or processes using Pb/Sn alloys and pure-Sn materials. (Pb/Sn should be avoided in the future due to environmental initiatives for lead-free interconnects.) However, when going ever smaller - down to 10µm - the bumps become more difficult to make. The options here are indium bumping, using In instead of tin in solder alloy bumps as well as pure-Sn bumps. When bumps must be made even smaller, one possibility is “automatic bumping,” in which etching is performed on the backside of thin wafers until the vias are exposed. These exposed via bumps can be used to create a “Lego-like” microconstruction.
Housing energy scavengers
Autonomous systems must provide their own power. The simplest and straightforward method for powering a SiC would be a rechargeable battery in one of the cube’s layers. To minimize space, a suitable choice is to directly deposit a thin-film battery on a chip. In terms of energy density, these batteries are very good, but their volume on chips might be too small to deliver the required power for SiCs. Materials for thin-film batteries also are not typically compatible with conventional IC processing, which might limit further development. In addition, connections for recharging embedded battery layers might require vias and interconnections of different types, which complicates process development.
A valuable option is to replace the battery with some type of energy scavenger. It must be noted, however, that scavengers often rely on random sources of energy, such as light, heat, or vibration. Energy is transformed when available, stored and used when necessary. Even if the source is not random - such as human body heat for health-monitoring devices - the output power from scavengers can be low and may not be sufficient for wireless transmission. In these cases, energy must be stored until there is enough power for all functions. These considerations often mean that the scavenger has to be associated with a battery. Some scenarios for future applications propose that a “super” capacitor could be used to store a charge when energy sources are relatively stable. From the system-integration point of view, the use of a scavenger simplifies the design because no battery recharge terminals are required.
Solar energy is by far the most efficient energy source for scavengers, but there are limitations on its applicability in 3D SiCs. Naturally, solar energy is not available in the darkness of night, and it cannot be used to power implanted applications that are not exposed to light. Also, when used, solar cells must be located on the outer layer of an assembled SiC, which might be incompatible with other packaging requirements. From the technology point of view, however, there are no major issues in processing because solar cells already are well developed.
Thermal energy scavenging generates power from the heat of machines or motors (as in a car) or the human body. Energy densities can be increased by using appropriate radiators for improved heat flow. Another approach is to position scavengers where heat flow is greatest (e.g., near an artery in a body area network application). A major challenge of integrating the thermoelectric generator in SiCs is to provide good thermal contact with the skin and an efficient heat radiation. This might require extra thermal connections between the layers of an SiC to provide an efficient thermal path for heat dissipation.
Sources of mechanical energy can be the movement of the body or vibration of machines. Typically, noninertial systems are used for scavenging. They are composed of a mass suspended by a spring to an accelerated frame. The energy dissipated in a damper is then transformed into electricity. The transformation mechanisms can be electrostatic, electromagnetic, or piezoelectric. A typical device layout includes three wafers (Fig. 4). The conversion of vibration to electricity is made by a variable capacitor, and a fixed charge is stored in a dielectric layer. There is no special requirement for positioning the scavenger within the cube, except the need to provide easy connections to the other layers.
MEMS in 3D SICs
The incorporation of microelectromechanical systems (MEMS) sensors and actuators requires careful design and integration as well as dedicated packaging technology. Unlike the other components - mainly featuring only electrical interconnections - sensors and actuators typically need to access the environment of the 3D SiC to operate properly. These device-specific input and/or output requirements affect the possible positions of sensors and actuators in the 3D stack as the choice for the optimal packaging and integration technology.
Biosensors, for example, need to have fluidic interfaces with the human body; therefore, positioning these sensors at one of the outer layers (bottom or top) of the 3D stack is essential. On the other hand, when using inertial sensors such as accelerometers and gyroscopes, there is more freedom for the stack design.
Moreover, the packaging of MEMS is a key factor. For miniaturization of stand-alone MEMS devices, often zero-level capping or wafer-level packaging technology is used. Thin-film capping uses surface micromachining techniques to cap the MEMS device during its processing, while in wafer-level packaging, a separate wafer or die is sealed to the MEMS substrate to protect the MEMS. Both packaging techniques can be combined within a 3D SiC stack. Depending on the position in the total stack, however, vertical electrical interconnections should be provided. This requires through-wafer via interconnects in the MEMS die and/or in the capping die. An electrical interconnect between the MEMS die and the capping wafers also is necessary. The latter must be compatible with the sealing method used for the MEMS packaging.
The optimum sealing technology, featuring the best performance and reliability at the lowest cost, is device-specific. Polymer sealing (e.g., using BCB) is a cost-effective way of cap sealing, which has been shown to be a very reliable and suitable packaging for RF-MEMS devices, for example [4]. Other MEMS, such as resonators or pressure sensors, require a fully hermetic sealing technology such as solder sealing or anodic wafer bonding. Given these different sealing and interconnection technologies with different temperature budgets, the process sequence for 3D SiC must be seriously considered.
Conclusion
Although 3D SiP results are increasingly promising and the first specific applications are reported, the industry still has a long way to go before general implementation of ultrasmall, autonomous, intelligent SiCs. The integration of different components with multiple functionalities requires well analyzed approaches, from the design level to manufacturing processes. Furthermore, an increased miniaturization toward stack heights in the millimeter range will only be possible after development of efficient ultrathin-chip stacking techniques. Obviously, autonomous systems provide their own energy; consequently, the development of process technology for self-contained power supply in ultrasmall SiPs is also of great interest. Finally, sensors and actuators, often incorporating MEMS in some areas of development, also call for special attention and a dedicated approach.
Acknowledgment
Lego is a registered trademark of the Lego Group.
References
- S. Stoukatch, et al., “High Density 3-D Stack Structure for SIP Solutions,” 14th EMPC, Feb. 2003.
- M. Reiche, “Ultrathin Wafers: Processing and Defect Issues,” Proc. SPIE, Vol. 4600, pp. 80-87, 2001.
- J.-J. Sun, et al., “High-aspect-ratio Copper Via Filling Used for Three-dimensional Chip Stacking,” J. Electrochem. Soc., Vol. 150, No. 6, pp. G355-G358, 2003.
- Oya, et al., “A Reliable and Compact Polymer-based Package for RF-MEMS Switches,” IEDM, pp. 31-34, 2004.
Koen Snoeckx is the scientific editor at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; ph 32/16-281-880, fax 32/16-381-637, e-mail [email protected].
Piet De Moor is the section head for wafer-level integration and packaging at IMEC’s integrated systems department.
Koen De Munck is a PhD student assigned to IMEC’s integrated systems department.
Eric Beyne is the program director of IMEC’s Advanced Packaging and Interconnect Center.