Technology News
03/01/2005
Porous low-k looks usable with sealing by etch byproduct and ALD TaN
The Japanese consortium Selete (Semiconductor Leading Edge Technologies) has demonstrated hp65nm interconnect modules showing good electrical characteristics and reliability with both porous CVD SiOC and porous spun-on MSQ, suggesting porous low k is at last on track for commercialization. By increasing the strength of the matrix structure and sealing exposed sidewalls with etch byproduct and an ALD TaN film, good mechanical strength was achieved; voids and copper permeation were eliminated.
The strength of porous MSQ films, as measured by Young’s Modulus, was not much influenced by pore diameter or alignment or other parameters, but correlated closely with calculated percentage porosity, Selete found. For any given porosity, strength was most effectively improved by strengthening the basic matrix material. Strengthening the S-O bonds more than doubled the Young’s Modulus, creating a porous MSQ with a k value of 2.3 and strength of 10GPa. Selete’s current material was made with a new spin-coating method, but similar strength in porous spin-ons has also been obtained with nanoclusters of silica monomers and by treating the porous film with gas after processing. This mechanical strength is about the same as that of the CVD SiOC now being used at 90nm, so it is a big advance toward manufacturability.
It is not yet clear how to best make porous CVD films, but so far the porous SiOC products made using silane or siloxane are not as strong as porous MSQ.
Another major problem with porous low-k materials has been etchant gases and metals permeating into the dielectric through its connected pores, creating voids and metal contamination. Selete solved this problem by sealing the exposed dielectric sidewalls with a byproduct of dry etching and a thin ALD film coating. MSQ with 33.6% porosity showed no copper permeation with a 1nm barrier, although it started to show up at 45% porosity and above.
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Selete found both porous MSQ and porous SiOC produced good results when sealed, each achieving a total effective k value of at least 2.7 in the demonstration interconnect module with 100nm lines and spaces, though the MSQ was stronger, and had a lower k value on its own (see table). Electrical performance of the porous SiOC almost exactly matched that of standard nonporous SiOC dielectric, as measured by via resistance. Electrical resistance of the porous MSQ sealed by ALD TaN showed about 2/3 less via resistance compared to sealing with the usual sputtered TaN/Ta film. There was also good reliability in wide copper interconnects, usually problematic with their stress-induced voids. Tests showed no change in via resistance after 500 hr at high temperature.
- Nobuyoshi Kobayashi, Selete, from SST partner Nikkei Microdevices
Immersion litho tests: No hidden problems
The next big step for 193nm ArF immersion lithography development will be fully equipped pilot lines in 2005. Immersion-related defectivity issues in functioning devices will be defined in those pilot lines.
This follows early split-lot tests of immersion lithography performed separately by IBM Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. in 2004. The two chipmaking rivals used the same 193nm prototype scanner from ASML Holding NV to expose one mask layer in working 90nm ICs. IBM’s test employed ASML’s AT:1150i (0.75NA) tool at the Albany NanoTech center in Albany, NY, to pattern an interconnect layer in 64-bit Power processors. TSMC’s immersion test, which exposed a polysilicon layer in the transistor gate stack of 90nm ICs, was performed by ASML in The Netherlands prior to the 1150i being shipped to Albany. IBM and TSMC completed wafer fabrication using conventional dry lithography and reported seeing no immersion-related defects in the split-lot tests.
Meanwhile, the installation and initial operation of an ASML XT:1250i 193nm (0.85NA) immersion scanner has begun at the Interuniversity MicroElectronics Center (IMEC) in Leuven, Belgium, which intends to use the tool to explore immersion lithography’s ability to greatly improve depth of focus (DOF) compared to dry 193nm scanners. IMEC and ASML have reported early results from the 1250i scanner, prior to its delivery, that showed a DOF of 0.7µm, which is 1.7× greater than obtained with an equivalent dry 193nm scanner (ASML’s AT:1250) using an NA = 0.85 lens. The first results from the 1250i, conducted inside ASML’s facilities, printed 70nm dense lines with a 6% attenuated phase-shift mask while operating at a scan speed of 450mm/sec.
A second 193nm immersion effort is also underway at IMEC to push resolution improvements using an ASML-built interference lithography system. This immersion interferometer will be used to print 200mm wafers with optics simulating >1.0NA exposures in an attempt to identify high-index fluids that could be used in 32nm and below processes . These alternative fluids will be needed to drive the “hyper” NA levels to 1.6 from a numerical aperture of about 1.3 in first-generation 193nm immersion scanners using water between the lens elements and wafer surfaces.
The installation of the ASML 1250i tool in IMEC’s 300mm development fab “should bring the required data to introduce immersion lithography in 2007 [for 65nm half-pitch processes],” says Luc Van den hove, VP for silicon process and device technology at IMEC. “This does not mean that some [participating] companies will not introduce immersion into production by 2006.” - J.R.L.