Diverse CMP needs require a dielectric selectivity platform
03/01/2005
It is likely the 45nm technology node will see the introduction of new materials and integration schemes. For the early adopters, the choice of materials, applications, and integration schemes is fragmented across the leading-edge IC manufacturers. One such path to addressing these fragmented, emerging needs - an adaptable oxide-to-nitride selectivity platform - is examined.
The introduction of copper and low-k dielectrics over the last couple of technology nodes has led to unanticipated but significant challenges. Looking forward, we will likely see new integration schemes and materials - such as ruthenium, hafnium oxides, and iridium and its oxides - play an important role in achieving improved performance.
These new schemes will rely on new combinations of old materials and/or the introduction of new materials to be successful, adding to the complexity and cost of development for both chip manufacturers and suppliers. IC manufacturers will need faster development of well-characterized materials from key suppliers and customized integration schemes. There will then be an additional challenge with regard to market fragmentation of the early adopters. These individual strategies/needs tend to converge as development programs get closer to solutions, but the cost of early engagement is a disjointed marketplace.
The complexities of the IC industry are not unique to one market segment. For example, logic and memory sectors alike are finding limitations that need technical solutions. To illustrate the diversity of these needs, some typical dielectric CMP applications will be discussed.
ILD/IMD planarization
For devices >130nm, dielectric CMP was relatively limited to two areas: interlevel dielectric/intermetal dielectric (ILD/IMD) planarization, and reverse mask shallow-trench isolation (STI) CMP. Both could be handled by relatively straightforward conventional silica-based slurries - the main requirements being low cost, planarization capability, and low defect levels. For most leading-edge ICs, however, dielectric CMP has become much more complex. Some examples of fragmented, novel dielectric CMP applications include:
- ILD/IMD. This requires planarization of deposited dielectric material (typically TEOS). The main considerations are good planarization efficiency and low defectivity.
- Selective PMD. This requires more than just improved planarization and defect levels; the polish step needs to be selective to nitride.
- Direct STI. For 130nm and below, reverse mask STI is not viable; as a result, most chipmakers have replaced this with a direct STI CMP step in which the polishing slurry must have a high selectivity to nitride. If the selectivity is too high, however, there is a possibility of dishing the underlying trench oxide. There also are large pattern sensitivity effects, with the dense areas typically clearing before the open areas.
- Metal gates. For the fully silicided gate and for replacement gates, a dielectric CMP step is required to expose the poly gate. An example of a process flow that exhibits step height control is fully described by researchers [1]. A two-slurry approach is proposed: a nonselective one of nitride vs. oxide, followed by a selective one of oxide vs. nitride.
To solve these divergent CMP problems, a tunable slurry platform has been developed. The platform is tunable for oxide-to-nitride removal rate selectivity, and has been developed from an understanding of the basic structure-activity relationships that exist among additives in the slurry and blanket films. The platform was developed by modeling the structure-activity relationships for the key additives in the slurry, and by creating a mechanism for oxide and nitride selectivities. A wide range of selectivities has been leveraged from this model (Fig. 1). An understanding of pattern dependencies on this platform technology has been realized and extended to enhance its applicability to diverse industry needs.
Applications
Two potential opportunities for end-user applications illustrate the practicality of the approach. First, the direct STI problem has typically been solved by using a high selectivity approach, as shown on the left side of the graph in Fig. 1. The historical problems with high-selectivity approaches have led to 1) large process and pattern sensitivities, 2) small over-polish windows, and 3) large oxide dishing. The issues with nonselective approaches to direct STI have been throughput and the inability to clear the remaining oxide. A new solution was developed in order to address the three key areas of user concern - throughput, planarity, and defectivity - relieving the bulk oxide overburden rapidly and automatically stopping on nitride with an inherent deceleration mechanism. Thus, final planarity at end-point is not controlled by topography or downforce, but by polishing time.
Using this selective deceleration mechanism, optimal planarity can be achieved for a direct STI CMP process by combining the benefits of high selectivity to nitride with the “slow” portion of the oxide time-dependent removal rate (Fig. 2). At the other end of the spectrum (Fig. 1), a solution to the gate-polishing problems similar to those described in [1] is achieved by extending the slurry platform to provide a nonselective approach. The cited process flow is reproduced in Fig. 3 and shows the enabling elements the two CMP solutions provide.
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Figure 3. Schematic of FDSOI device fabrication, shown in gate cross-section. 1) Starting SOI, isolation, and gate oxide growth; 2) poly-Si gate and oxide hardmask deposition, gate lithography, and etch; 3) extension implant; 4) spacer formation; 5) selective silicon epitaxy raised source/drain; 6) source/drain implant and activation anneal; 7) source/drain silicidation with Co; 8) nitride and oxide liner deposition; 9) gate expose CMP; 10) gate silicidation with Ni. (Reprinted with permission from [1], 2003 IEEE)
The first CMP solution is shown after step 8 yielding step 9, known as the poly-gate exposure step. This is where a nonselective slurry works well to provide the required planarity control. The second CMP solution comes after step 10 and provides a path to the silicided gate-polish step. This CMP solution needs to be selective to oxide to achieve the high planarization efficiency without loss of gate thickness. This example is only one potential integration option for addressing the performance concerns of metal gates. Other viable solutions exist with equally challenging problems. In other applications (not discussed here), a high reverse-selectivity (high nitride-to-oxide) slurry allows pursuit of other novel integration schemes.
These solutions can only be successful by providing a level of planarity and defect control required for that particular technology node. The rate of planarity and defectivity improvements are established to keep pace with the optical resolution requirements of lithography and the constant yield requirements through device shrinks. Often the road to improved planarity can lead to higher levels of defectivity and vice versa. Optimal solutions are generally sought through an understanding of these fundamental trade-offs and finding the appropriate level of balance to meet performance factors. Due to greater sensitivity of defects to product yield, a stronger emphasis often is placed on both the baseline levels and variability of defect control to hit the yield targets.
Many additional challenges exist along the way, from metrology sensitivities, to finding appropriate classifications, to understanding the key metrics for performance prediction, all of which lead to difficulties in providing appropriate defect targets for the end-user dependent patterns and films. By addressing these issues and understanding the formulation control, however, enabling solutions can be leveraged through the development of platform technologies.
Conclusion
Examples show how a tunable slurry platform can be adapted to meet diverse integration needs. CMP solutions can reduce the overall cost by reducing additional process steps and focusing on yield-impacting performance predictors. This mechanistic view of solution development ultimately cuts down on qualification time for the end user and reduces time-to-market as well. The complexities of the IC industry are increasing; adaptable, well understood, and robust solutions are needed to address performance constraints that negatively affect yield.
Acknowledgment
SiLECT is a trademark of Cabot Microelectronics Corp.
Reference
- J. Kedzierski, D. Boyd, Y. Zhang , M. Steen, F. Jemin, et al., “Issues in NiSi-gated FDSOI Device Integration,” IEDM, 2003.
Gautam Grover is global marketing director at Cabot Micro-electronics Corp., 870 Commons Dr., Aurora, IL 60504; ph 630/375-5567, e-mail [email protected].
James Dirksen is director of enabling technology at Cabot Micro-electronics Corp.