Asian technologists’ 45nm outlook
02/01/2005
Toshiba looks to cooling technology to reduce power usage
Toshiba plans to start volume production of high performance 65nm devices this month or next, followed by the low-power version next year. We’ll then start 45nm (hp65) production in early 2007.
We expect to use ArF immersion for 45nm. We may somehow extend that as far as 32nm, but will probably have to switch over to EUV or e-beam technology before that. Currently, the key issue is to determine by simulations whether we can make patterns with sufficient margin using OPC and phase-shift masks.
At 45nm we expect to use HfSiON high-k film for low-power devices. HfSiON has the problem of reducing mobility, but we will combine it with strained silicon. We are still studying whether or not to introduce metal gates at the same time as high-k, since problems remain with stability and process integration.
We plan to use porous low-k from 45nm, and we are evaluating changing over to a spin-on process. We’ll introduce strained silicon at 65nm for some low-power devices, using locally induced strain.
It used to be possible to make low-power, standard, and high-performance devices just by slightly changing the oxide film, but now we have to develop completely different devices within the same generation, reducing supply voltage to 0.75V for high-performance products, for example, while increasing it to 1.1V for low-power devices. It’s not clear, however, if we can continue to do this in future generations. We’re advancing with parallel development of the alternative approach of reducing operating temperature. If we cut operating temperature from current levels of around 85°C down to around room temperature, we could reduce the supply voltage for low-power 45nm devices.
We won’t need SOI for 45nm, but it may be necessary to introduce it at 32nm. However, the advantage of SOI declines as the silicon gets thinner, as its parasitic resistance increases. It may be necessary to combine it with 3D transistor structures.
Masukazu Kakuma, SoC technologist, Toshiba Semiconductor
TSMC remains conservative on introducing new materials
TSMC isn’t making any big changes in materials at 65nm, though we will change the silicide from CoSi to NiSi, introduce locally strained silicon, and start testing ArF immersion lithography. At 45nm, we are looking at changing to high-k and metal gates.
We have just started to evaluate the immersion tool from ASML we installed in October, but we hope to extend its use through the 32nm generation. But different lithography technology will definitely be necessary from the 22nm node, either immersion with a liquid other than water, e-beam, or EUV. E-beam’s once problematic throughput has improved enough that its potential is much improved.
Introducing both high-k and metal gates at the same time in the 45nm node would be extremely risky. At first, we may use metal gates and conventional dielectric in high-performance devices, and conventional gate materials with high-k dielectric for low-power devices.
We’re using locally induced strained silicon. We introduced a transistor capped with a SiN layer at 90nm. At 65nm, we’re evaluating introducing strain in shallow trench isolation, spacer, and source-drain sites.
We were the only foundry to use SiOCH with a k value of 3 at 130nm. We will continue to use the same material at 90nm and 65nm, but plan to offer the option of a porous material with a k of 2.5-2.7.
Shang-yi Chiang, SVP of R&D, TSMC - SST partner Nikkei Microdevices
Fujitsu focuses on metal gates, NEC to start with polysilicon
Fujitsu plans to introduce low-power devices with both high-k and metal gates in 2006, about a year ahead of the roadmap. “Polysilicon can be used with high-k dielectrics only for a generation or two, so it’s not worth investing development resources in it,” argues Toshihiro Sugii, Fujitsu’s director of advanced LSI development. Though no single metal has yet been found that works for both pMOS and nMOS, Fujitsu researchers say they can control the threshold voltage of MO by adding N, to achieve suitable levels for pMOS for both high-performance and low-power applications, though so far for only low-power applications for nMOS.
 Putting a barrier layer between the NiSi and the high-k dielectric controls threshold voltage pinning. (Source: Fujitsu) |
They’re also working on the potentially more straightforward approach of using fully silicided polysilicon, and report they’re solving the threshold voltage pinning problem caused by defects at the interface of the two materials by putting a barrier layer with no Si or O between the NiSi fully silicided gate and the high-k dielectric.
With its emphasis on low-power products, NEC Electronics plans to first start using high-k dielectrics with polysilicon gates in 2006. It has shown it can achieve wide control of threshold voltage with a dual metal-gate structure using TiN for pMOS and Ta for nMOS, but the metal reacts with the HfSiO dielectric when heated, so researchers say they’ll need to test many more materials to get practical metal gates. But with progress on preventing threshold voltage pinning, NEC says it, too, is looking at fully silicided polysilicon for its low-power devices in 2008.
M. Kimura, SST partner Nikkei Microdevices