Thermal budget reduction drives RTP beyond the 45nm node
02/01/2005
Limits on thermal exposure are being driven by advanced node requirements and depend on the device’s physical state at any given point, as well as the kinetics of the undesired phenomena that may arise from heat treatment (e.g., atomic diffusion, chemical reaction, defect formation, or phase changes). Rapid thermal processing (RTP) limits such negative side effects by minimizing thermal exposure, while providing a highly controlled ambient that eliminates contamination. Recent trends in RTP thermal budget reduction include “hotter and faster” processing that enables advanced ion-implant annealing processes for forming ultrashallow junctions (USJ), and the increasing use of RTP at relatively low process temperatures (<500°C) needed for advanced silicides.
 Figure 1. Thermal budget criteria for various degrees of B diffusion and for electrical activation of 50% of the carriers available from a low-energy B implant [1]. |
Figure 1 shows the impact of thermal budget on doping profiles through estimates of boron diffusion associated with a range of heating conditions. The curves were calculated using [4D(T)t]1/2, where D(T) is the intrinsic diffusion coefficient for boron at process temperature T and process time t. Diffusion length can be much larger because of enhanced diffusion effects, but these curves suggest maximum thermal exposure limits for boron doping. For fabrication of advanced devices, all thermal processes above ~750°C will have to be performed with RTP. Thermal budget after source/drain formation and gate activation must be even lower; otherwise, metastable doping levels tend to deactivate.
USJ formation
USJs are formed through low-energy ion implantation followed by RTP annealing. With scaling, the general trend toward higher annealing temperatures and reduced anneal durations has arisen from the difference between the thermal activation energy for dopant diffusion and that for electrical activation (Fig. 1). The dashed curve represents the time taken to activate 50% of the carriers that can be introduced by an implant of 1015 B/cm2 at 250eV [1]. This process has an activation energy of ~4.7eV, whereas that for intrinsic B diffusion is 3.46eV, so electrical activation is kinetically favored over diffusion at higher temperatures; annealing for a shorter time at a higher temperature reduces diffusion.
Figure 1 suggests that limiting diffusion to only ~1-2nm requires an anneal of ~1 msec at a temperature just below silicon’s melting point. Millisecond annealing is possible through selective heating of the wafer surface. For example, a pulse of energy from an array of flash lamps can generate a large temperature rise at the wafer surface followed by fast surface cooling, with the wafer’s bulk acting as a heatsink. This offers a solution for advanced USJ without requiring extensive changes in the process integration scheme.
The fRTP process
Figure 2 compares junction depth (XJ) vs. sheet resistance (RS) results from conventional RTP spike anneals to those from millisecond annealing with the flash-assist RTP (fRTP) approach [2]. fRTP annealing combines a fast ramp to an intermediate temperature with surface heating by a pulse of energy from an array of water-wall flash lamps. The study also compared results from samples doped by conventional beam-line implantation with BF2 and those implanted by plasma doping with a BF3 source gas. Being able to adjust intermediate temperature during the flash-assist process and the magnitude of the temperature jump induced by surface heating allow tuning of diffusion relative to the degree of activation. This may prove useful for tuning overlap with the channel and reducing problems in completely diffusion-free anneals that can exacerbate line-edge roughness effects at the gate electrode.
The elevated intermediate temperature also decreases the pulse energy needed for surface heating, reducing stresses and pattern effects. The process meets ITRS XJ/RS requirements down to at least the 45nm node; the approach is expected to extend to 32nm. Figure 2 includes predictions of the XJ/RS trends expected for box-shaped doping profiles with various concentrations of electrically active boron. Concentrations for two of the curves were chosen to match the results from spike annealing and fRTP. Electrical activation is improved >100% with fRTP.
Silicide processing
Thermal budget reduction also is needed in silicide processing, partly because of the move to NiSi as the contact and gate silicide. Various NiSi integration schemes have been considered, but a consensus has emerged on a two-stage process, with an initial 300-350°C anneal, followed by etching of unreacted metal and a second anneal at ~450°C.
 Figure 3. Low-temp heating cycles are important for NiSi formation (performance of Mattson Technology’s Helios RTP system). |
Figure 3 shows how lamp-based RTP temperature measurement and control technology enables closed-loop temperature with fast ramp rates, even in this low-temperature regime, critical because the very fast diffusion of Ni in Si demands precise control of thermal exposure. Once NiSi is formed, its thermal stability limits require that subsequent process temperatures do not exceed ~600°C. Increased use of SiGe in contact regions means that NiSiGe materials are becoming important, and their thermal stability limits are even lower, <~500°C. Other metals, such as platinum, may be needed to improve thermal stability. Backend process temperatures also are being lowered because of the increasing significance of dopant deactivation on electrical conductivity. Advanced doping processes produce concentrations above the solid-solubility limit, and thermal exposure can lead to deactivation, which undoes the activation anneal’s good work.
Acknowledgments
Flash-assist, fRTP, and Helios are trademarks of Mattson Technology Inc.
References
- R.B. MacKnight, P.J. Timans, S.-P. Tay, Z. Nenyei, in RTP 2004, p. 3, IEEE, Piscataway, 2004.
- J. Gelpey, D.F. Downey, S. McCoy, E.A. Arevalo, “Optimized Doping and Activation for Ultra-Shallow Junctions for 65nm and Beyond,” Proc. Mat. Res. Soc. Symp. 810, 2004.
Contact Paul J. Timans at Mattson Technology Inc., ph 510/492-5992, e-mail [email protected].