‘Design for manufacturing’ spreads
02/01/2005
Solid State Technology asked design automation managers how DFM software is shifting the responsibilities for wafer yields.
‘Yield-aware’ designs target production issues
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Mark Miller, VP, marketing and business development for DFM, Cadence Design Systems Inc., San Jose, CA
As designs transition to smaller processes, manufacturing effects must be considered earlier in the design cycle. Although process engineers are well aware of the need to address nanometer effects, both manufacturing and design operations will face a greater need to cooperate in anticipating manufacturing issues earlier in the product development cycle. By addressing manufacturing yield issues throughout the design chain, as well as in production, chipmakers can increase both yield and profit opportunities.
Until recently, most IC designers felt that yield was the responsibility of the manufacturing team. Maximizing yield was important to designers, but their responsibility generally ended at the point when the design met physical and electrical design rules. This division of responsibilities is no longer valid with mainstream process technology progressing below 130nm.
Rapid advances in IC design and process technology have brought several trends that negatively affect chip yield. Manufacturers are finding that shrinking feature sizes, larger chip designs, and expanding design complexity are resulting in severe yield losses due to manufacturing effects, signal integrity issues, and electromigration problems. Designers are also being forced to handle higher clock speeds, and at 500MHz or above, critical clock and signal paths take on distinctively analog behaviors. To address this, digital designers must think like analog designers, requiring more complex design techniques to meet chip performance requirements. To compound matters, lower supply voltages are critical to address small process geometries and low power requirements, but these trends result in lower noise margins and increasing signal integrity problems.
Engineers can substantially enhance yield by using yield-aware design methodologies that address design for manufacturability (DFM) early and throughout the development cycle. In the past, design awareness of manufacturing was focused in design-rule check (DRC) software tools and in parasitic extraction. Because DRC could provide a sufficient representation of manufacturing concerns with earlier technologies, semiconductor manufacturers could rest assured that designs passing DRC were manufacturing-ready. Similarly, earlier parasitic extraction methods could reliably produce results based on a general representation of the target process technology.
For emerging nanometer technologies, however, these earlier methods are inadequate. For example, in the past three years or so, leading manufacturers recognized the need to represent the effects of process distortions in extracted parasitics. At the same time, design tools complement more sophisticated lithography methods such as phase-shift mask (PSM) techniques. New tools help physical designers identify structures that might cause PSM problems due to orientation or spacing conflicts. In fact, emerging capabilities will allow designers to simulate the effect of advanced lithography processes on the final shapes written on wafers.
Among emerging tools and development methodologies, those that share a common database are best suited for enhancing yield, particularly for designs below 130nm, because yield-reduction mechanisms are highly interdependent and influence IC performance parameters. At present, the industry lacks a common database definition that is broad enough to accommodate both design and manufacturing, although efforts such as the Universal Data Model from the Silicon Integration Initiative offer promise as the basis for an effective solution.
Process variations also have become more significant at smaller geometries, and consequently design-centering is needed on most cells to optimize yield. Another factor to consider is the need for new optical lithography techniques at 65nm and beyond. These techniques create a new level of interdependence between design and lithography. Effects of mechanical process steps, such as CMP, etching, and deposition, also must be accommodated, and the design sensitivity to process variations must be understood.
For designers, the realities of advanced manufacturing dictate a growing need to expand current notions of design constraints based on timing or power concerns to include limitations arising from new yield challenges. Making physical corrections by post-processing GDS-II or mask data happens too late in the design flow and will not catch all of the yield-reducing problems.
Today, the design costs of a typical 130nm IC approach $10 million or more, with mask costs alone nearly $1 million. At 90nm, companies find that less than half of IC designs operate as expected and more than half need a complete mask “re-spin” for acceptable yield and performance. This points to the fact that designers must consider manufacturing yield and DFM issues throughout the design cycle. Integrated design methodologies must be used that help engineers design with yield in mind.
Contact Mark Miller at Cadence Design Systems Inc., 2655 Seely Ave., San Jose, CA 95134; ph 408/894-2961, fax 408/944-0747, e-mail [email protected].
Mask synthesis becomes vital for production
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Srinivas Raghvendra, senior director, DFM business development, Synopsys Inc., Mountain View, CA
Today’s advanced semiconductors are being manufactured with features that are smaller than the wavelength of light used to pattern them. This seemingly impossible feat is achieved through resolution enhancement techniques (RET) implemented with mask synthesis tools. Mask synthesis has become a critical component of a design for manufacturing (DFM) solution, yet it is not particularly well understood by most designers.
At larger process geometries, mask synthesis was a simple step. As silicon features shrank, however, the need for mask synthesis became more acute and the process became more complex. This has put mask synthesis in the critical path of volume manufacturing.
The gap between IC feature sizes and photolithography wavelengths emerged at the 0.18µm process node and widened at 0.13µm, making advanced mask-synthesis techniques a necessity. At 0.13µm and below, optical distortions and other lithographic effects cause larger features to deform and smaller features to disappear altogether. The resulting variations can significantly decrease device performance or lead to yield loss.
Mask synthesis has evolved to address these problems by applying RETs, such as optical proximity correction (OPC) and phase-shifting masks (PSM), but these technologies bring some complications, including larger mask-data file sizes and increased mask-write times and costs. RETs have become a key differentiator for manufacturers. With the same equipment line, fabs can get a different quality of results depending upon the type of RETs used and the “recipe” for RETs. The ability to customize and protect manufacturing process intellectual property (IP) has become an important issue in RETs.
Mask synthesis steps produce an enormous amount of data. This has caused significant increase in the turnaround time (TAT) for mask manufacturing. The breakthrough solution to this problem has been distributed processing. The idea is simple: Divide a design into hundreds of pieces, and then run each piece concurrently on a separate processor. The final results are then combined. While conceptually simple, implementing a software tool to be scalable to hundreds of processors is a complicated challenge. Currently, Synopsys’ OPC tool, called Proteus, can run on more than 1000 processors. While most OPC processing today requires tens, not thousands of processors, the ability to use more processors, if necessary, means that TAT will not pose a problem well into the 45nm node.
The problem of large data output can be mitigated by doing “smart” or “design-driven” OPC. By applying design-intent information to the mask-synthesis tool flow, a user can perform design-driven OPC, which applies only the minimum amount of OPC necessary to meet lithography goals [i.e., low tolerance on critical dimensions and more relaxed tolerance for noncritical features]. The results are significantly smaller file sizes and reduced mask-write times without affecting chip performance. But for this to be possible, the link between design and manufacture will have to become tighter, and design information should be accessible at the mask synthesis step.
In addition to design information flowing “down” to mask synthesis, design rule information must flow “up” from manufacturing operations and foundries. In addition, information about the scanner characteristics and resist and etch behavior is needed to create the correct “recipe” for mask synthesis. However, this wafer fabrication information must also flow further up the chain to design steps, such as place and route. For example, certain illumination schemes may place specific requirements on the place and route of the design. In this case, the stepper illumination scheme information must flow up to the place-and-route tool and place some restrictions on the design style.
Because process engineers build different models for different technology nodes, layers, and sometimes regions within a mask layer, it is critical to customize the model and the correction recipe to achieve quality results. A highly programmable mask-synthesis tool allows engineers to optimize their own processes without having to go back to tool vendors, thereby giving them the flexibility to tune models directly while protecting specific process information and IP.
With DFM becoming a critical component in wafer fab yields and device performance, the need for tighter links between manufacturing and design steps is growing. The most advanced design tools already have begun to take into account both mask synthesis and manufacturing process issues. Looking ahead, it is clear that further improvements will be needed to link design with manufacturing and create new hand-in-hand approaches for continued success in the semiconductor industry.
Contact Srinivas Raghvendra at Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA 94043; ph 650/584-5000, fax 800/541-7737, e-mail [email protected].