Putting the Roadmap to work
01/01/2005
Solid State Technology asked a chipmaker and an equipment supplier to comment on how the Roadmap affects manufacturing strategies.
'Grand challenges' can help differentiate ICs
 Seshadri Subbanna, director, SOI technology development, Systems & Technology Group, IBM Corp. |
Over the years, the International Technology Roadmap for Semiconductors (ITRS) has been an essential guide and trusted reference point for the product and technology plans of semiconductor manufacturers. The Roadmap helps identify semiconductor technology requirements and facilitate cross-industry advances in the design and manufacture of integrated circuits.
Leading-edge semiconductor chip manufacturers interact with the Roadmap in two ways. First, they provide input that helps shape it. Second, they use the Roadmap and the combined input from equipment manufacturers and other chip manufacturers to determine how to provide leadership in their selected businesses and maintain differentiation.
An integrated view from chip manufacturers is necessary to generate equipment makers’ support for new generations of process and test equipment because of the significant investment required. Large chip manufacturers also forge alliances with critical tool manufacturers to ensure their own roadmaps are interlocked. For development of new processes, especially in the case of innovation, a chip manufacturer with its own research labs may be able to provide IP that helps jump-start tooling for new processes.
The addition of a high-performance analog and mixed-signal roadmap has helped fill out the ITRS and provides chip designers and IC users with an additional benchmark for their own designs and plans with respect to power and performance.
Historically, classical scaling has been maintained in conjunction with the ITRS by shrinking lithographic dimensions as well as process dimensions, such as junction depths and gate oxide. Recently, a number of “grand challenges” surfaced in the Roadmap during the transition to 90nm.
First and foremost, it is clear that traditional scaling cannot deliver the expected performance and power improvements due to issues with device variability and subthreshold current. This has created an increased need for innovation to maintain scaling, with divergent process paths. The emergence of silicon-on-insulator has provided a different power-performance envelope. In the midst of this, cost and yield crossover are critical to selecting a new technology for design.
While daunting, these challenges present an opportunity for individual design and process companies to differentiate themselves by providing leading-edge solutions, thus making it easier for a chip manufacturer to improve its yield or get better performance. An example is power-efficient or power-aware designs. If the right kind of devices or “hooks” are provided, it is possible to design a radically more power-efficient chip. This may be critical in moving to a cheaper package and providing cost leverage. In the case of analog mixed-signal designs, a superior enabling technology that offers better or easier circuit design could be an important differentiator.
At the high-performance end, the investments required for leadership are substantial. To be a leader requires consistent research investment to stay ahead of the pack, as well as the ability to forge alliances with tool and process manufacturers to provide an all-around design solution to internal or external chip designers. Given the challenges with power scaling and lithography at 90nm and beyond, the time-to-market advantage will lie with a large manufacturer capable of supporting the high level of investment required.
Two-year vs. three-year cycles. Ultimately, it is unlikely that an individual chip manufacturer or process tool company will be able to address all of the grand challenges involved in getting a leading-edge chip to market. Large, vertically integrated manufacturers such as IBM will be able to invest in the right combination and schedule of design, test, enablers, and process technology to provide an early solution. This is likely to result in vertically integrated manufacturers maintaining a two-year cycle of competitive process introduction, while even high-performance foundry manufacturers are likely to end up on a three-year cycle.
In the analog and mixed-signal world, a close coupling between enabling and process is even more critical. Many of the changes made by fabs for yield improvement in digital circuits could cause changes in analog circuit performance and chip yield if all the right analog parameters are not carefully monitored, measured, and modeled on a routine basis.
In summary, a leading-edge chipmaker can maintain process leadership by providing critical input to the ITRS along with other chipmakers - to drive innovation in process and enabling technologies, particularly in this era of extremely complex and interactive process and design scaling. At the same time, by providing a holistic integrated solution that addresses many of the ITRS’s grand challenges, a more vertically integrated manufacturer can remain ahead of the Roadmap for critical chips and provide leadership and differentiation.
Seshadri Subbanna is director of SOI technology development and high-performance server technology in the Semiconductor Research and Development Center of the Systems & Technology Group at IBM Corp., Hopewell Junction, NY; ph 845/892-5422, e-mail [email protected].
Economic reality drives roadmap strategy
 Sass Somekh, president, Novellus Systems Inc. |
For several decades, the ITRS has provided common ground for discussing technology needs and timing across the semiconductor industry. While the timing for insertion of a particular technology might vary from company to company, the Roadmap served to identify needs and quantify broad technical requirements. It was an appropriate response to solve customer problems in an expanding sector.
Today, the landscape clearly is changing as the industry starts to mature. The electronics food chain remains very healthy, and new product applications continue to drive silicon content up in end-market devices: data from VLSI Research and Dataquest indicate that IC units have shown a healthy 10.3% compound annual growth rate (CAGR) from 1983 through 2003.
Since 1996, though, average selling prices generally have been declining, a function of the emergence of the Asian foundries and increased competition in chipmaking markets. Looking at this from the semiconductor manufacturer’s perspective, revenues/area of silicon essentially have flattened out. As a result, the semiconductor industry growth rate is declining dramatically. As recently as 10 years ago, the semiconductor industry was returning a 10-year rolling CAGR of 15% to 20%. In 2004, that figure was reduced to ~5% to 10% (per VLSI Research/Dataquest data).
Hefty price for innovations. Even as top-line revenue growth flattens, technological change continues to accelerate. The convergence of device shrinks, new materials, and wafer-substrate size increases have created a “perfect storm” of technological innovation that is coming at a significant price. Technologies such as copper metallization, low-k dielectrics, high-k gate oxides, silicon-on-insulator (SOI), and strained silicon lattices all require a tremendous influx of engineering resources and money to characterize, understand, and develop into new unit processes that can be integrated into a process sequence.
Now, as top-line revenue growth slows and technology investment costs rise, the chipmakers’ profitability is affected, and these companies can’t afford to spend as much on capital equipment. Data from VLSI Research and Dataquest suggest that the decade of the 1990s, with capital expenditures ranging from 20%-35% of revenues, appears in retrospect to have been an anomaly. With top-line revenue growth rates reduced to 10%, the semiconductor manufacturer’s capital-equipment depreciation expense must decrease from an average of 24% of revenues to about 16.5% to achieve the same return on equity.
It is evident that as the size of the market shrinks, competition will increase among its participants, and equipment suppliers will naturally be less willing to exchange information in efforts such as the ITRS. It should also be evident that with less money to spend, the semiconductor manufacturers’ natural reaction will be to extract more productivity and equipment lifetime from their assets. As a result, the burden will fall on process equipment suppliers to provide more technology for lower cost. Our product roadmaps, then, must address the concurrent needs for both technology and productivity. Platform extendibility is a key enabler for meeting these dual roadmap requirements, since without superior technology, platform extendibility beyond one or two nodes is typically not possible.
With our roadmaps at Novellus, we’ve tried to address this challenge of platform extendibility across all of our product offerings. A number of our technologies originally introduced at less advanced nodes (e.g., 0.25µm or 0.18µm) have been extended to the 45nm node without re-engineering the platform. In the chemical-vapor deposition (CVD) arena, innovations such as pulsed nucleation-layer technology for tungsten plug fill have enabled us to produce void-free fills in 45nm structures, without sacrificing the inherent productivity of a CVD approach. Similar innovations are being pursued with advanced dielectric gapfill in subtractive aluminum manufacturing processes to keep these highly productive CVD deposition rates.
In considering product roadmaps, process equipment suppliers must understand how the economic picture has changed for the semiconductor manufacturing industry, and the impact on the end users. Technology roadmaps and product-development roadmaps must adhere to the new edict of technology and productivity if the supplier is to be successful in the long term. The continuing success of roadmaps is also dependent on broadbased participation by the industry, which, in recent years, has been weakening. In an era of increased competition, industry initiatives such as the ITRS will only be successful as vehicles for the exchange of precompetitive information, and only if the entire semiconductor manufacturing community is well represented in the discussion.
Sass Somekh, PhD, is president of Novellus Systems Inc., 4000 North First St., San Jose, CA 95134; ph 408/943-9700, e-mail [email protected].