Technology News
01/01/2005
Consumer gearmakers choosing SiP over SoC
While fab folks are still mostly only talking about design for manufacturing and 3D chip stacking, the assembly world is actually doing it, and getting significant improvements in system-in-a-package (SiP) cost and performance. Increasingly, SiP is no longer just a packaging technology for a quick, low-volume stopgap until a full-performance system-on-a-chip (SoC) can be developed. Japan’s major makers of consumer electronics gear are choosing SiP instead of SoC as the best high-speed, low-cost manufacturing solution for a crowd of new products.
The SiP may now match SoC performance. Sony reports a prototype unit attaching a microprocessor face-to-face to a 64Mbit DRAM with bumps with resistance of 14mΩ/bump and capacity of 50fF/bump, the same as about 1mm of interconnect on the chip. At 123MHz, the SiP transmitted data at SoC-type rates of 160Gbit/sec. Delay time was about the same as the SoC. Matsushita Electric Industrial plans to use an SiP for the high-speed memory interface for its digital televisions for 2005-2006.
 With higher demands on memory, consumer products increasingly use SiPs, not SoCs. (Source: Renesas Technology) |
Driving the change is systems suppliers’ desire to differentiate their cell phones and digital cameras not just on the traditional price, size, and time to market, but on a range of distinctive complex features like better sound and better pictures. Combining the desired analog, logic, and massive memory functions, all made with different processes, requires one very large and costly SoC, so the SiP alternative looks more appealing.
But designing chips especially for the best packaging connections has notably improved performance. SiPs used to just combine off-the-shelf chips, but now executives at Matsushita, NEC, Fujitsu, and Elpida all say 90% or more of their SiPs use specially designed chips. The chips are specifically sized for convenient stacking and attachment. Their contact pads are optimally placed to allow the most direct connections between devices. And input/output buffer circuits are optimized for data transmission speed between chips.
The optimized designs also further reduce costs, sometimes to less than those of separately packaged chips. The simpler connection patterns allow the chips to be put on cheaper substrates with fewer layers, using glass-epoxy substrate instead of multilayer buildup board. Built-in self test elements further cut costs by limiting the number of connections to the outside.
Although optimizing chip design for integrating into an SiP improves performance and reduces costs, it also now takes the same nine months to a year to bring an SiP to market as it does an SoC.
- H. Asakura,
SST partner Nikkei Microdevices
Consortium prints SiP substrates on demand with ink-jet technology
Japan’s Program Jisso Consortium is showing off a working SiP with interconnections made by ink-jet printing. The group of Japanese companies aims to cut the time it takes to make prototype SiPs down to half a day.
Instead of making a mask from the CAD data and exposing and etching the patterns, which can take two weeks to a month, the group prints the circuit patterns and the dielectric layers directly from the CAD data to the substrate with an ink-jet printer in a few minutes.
The circuits are printed with paste containing nanoparticles of silver 5-10nm dia., which is then heated to melt the metal. Components are arranged on adhesive tape, then encapsulated in resin. The unit is turned over and the tape peeled off to expose the surfaces of the devices. Then, layers of metal circuits and dielectric are printed on top as needed, and other components mounted face down on top of those circuits. It takes one to two minutes to print the unit.
The prototype SiP has 50µm circuits connecting an LED with IC drivers and assorted passive components, processed at 230°C, with conductivity of 3µΩ-cm. The LED lights use 0.49mA and 2.5V.
Researchers say they aim to mass-produce substrates with 20-30µm circuits by 2006, although they admit problems remain with cracking and precision.
Among the consortium’s 10 members are Ulvac, Harima Chemicals, Osaka U., Atomnics Laboratories, and Sharp Takaya Electronics Industry.
- H. Asakura,
SST partner Nikkei Microdevices