Issue

ITRS Special Report: Interconnect, Process Integration, and Wafer Cleaning

01/01/2005

Concern shifts to resistivity of copper due to scaling-induced scattering

In even-numbered years, such as 2004, the International Technology Roadmap for Semiconductors (ITRS) undergoes an update in preparation for a full revision the following year, as is expected in 2005. Solid State Technology worked with leaders in various technical working groups of the 2004 ITRS to highlight the most significant updates in the new edition of the industry’s roadmap, as well as major challenges to be addressed in the 2005 revision. This report summarizes modifications and challenges identified in process integration, wafer cleaning, and interconnect.

The Interconnect chapter of the 1994 National Technology Roadmap for Semiconductors laid out the anticipated needs for conductors and dielectric materials over a 15-year horizon. Ten years after the publication of that document and four major ITRS editions later, the 2004 update highlights a series of new challenges around the use of copper wiring, a consequence of the deteriorating resistivity of copper wires with decreasing linewidth.

The role of the interconnect wiring system is to distribute clock and other signals to the various functional blocks of the IC, along with providing the necessary power and ground connections. The local wiring has never been considered an RC delay challenge because of the short wiring lengths used to connect transistors within an execution unit on ICs. The grand challenge has always been the delay associated with long, global wires.

In the 2004 update Interconnect chapter, however, the increasing resistivity of copper wires, as linewidth decreases, is highlighted (see Figure). Some of the global wiring challenges have been met by design changes, the use of repeaters, and especially the reverse or hierarchical scaling approach, which allows wider pitches at higher wiring levels. Debate continues around the use and definition of a metal one (M1) pitch. Some recent publications by logic device manufacturers suggest that M1 and intermediate wiring pitches may be scaling at a rate that exceeds that projected in the Roadmap. This may also be a result of confusion over the difference between “noncontacted” M1 pitch, as widely used in technical conferences, and the contacted pitch used in the ITRS. This distinction is blurred, though, as all logic manufacturers strive to achieve a borderless contact and via system.

Figure. Smaller copper linewidths result in higher resistivity.Click here to enlarge image

A model that incorporates copper resistivity has been used to generate a series of new metrics in the interconnect technology requirements tables of the 2004 update. The model for calculating increases in Cu wire resistivity due to electron-scattering effect is

ρ(W) = ρ0[1 + (λ/W)[3/4(1 - p) + 3/2(r/1 - r)]]

where ρ0 = constant (1.9µΩ-cm@300K); λ = MFP (mean free path of charge carriers) = 3.4×10-6cm; W = wire width (cm); r = probability for reflection of electrons at the grain boundaries = 0.2; and p = portion of electron specularly reflected from the wall (surface or interface).

In the MPU technology requirement tables, interconnect delay (picoseconds) is calculated for a 1mm copper wire, assuming width-dependent scattering (as described earlier) and a conformal barrier of thickness specified in the tables. The probability of reflection at grain boundaries (r) was selected at 0.2, a consensus of the many groups working on these measurements. The table ([click to download]) shows selected portions of the updated near-term MPU interconnect technology requirements. Good correlation has been found between experimental results for the resistivity rise and these selected parameters.

It is apparent that the impact of scattering on the copper wiring produces interconnects with an effective resistivity that exceeds the ITRS target of 2.2µΩ-cm in the next two years. Industry efforts need to focus on this aspect of the Roadmap challenges.

Low-k stays on track

For the first time in the last 10 years, the Roadmap’s low-k portion was unaltered (k-value targets not delayed) with respect to the prior edition. Small changes were made to the box shading for bulk and effective dielectric constant over the next 5 years, recognizing that materials that deliver an effective k = 2.7 are in production today and those material systems that will deliver an effective k = 2.4 are expected to be available with manufacturable solutions in the next 3 years. Again, the effective k value is projected from a model that is based on the thickness of the bulk dielectric material, the thickness and k value of any dielectric barrier or masking films, and an estimate of any effects on capacitance due to processing. Thus, a range of values is shown in the tables. Red shading remains for the long-term years (2010 and beyond), where manufacturable solutions for materials with a dielectric constant <2.1 are still unknown.

The surface preparation technology requirements tables provide guidance to process tool designers regarding the maximum permissible change in dielectric constant as a result of any strip or clean steps. Concerns over sidewall damage of the porous low-k films have resulted in a great deal of effort on minimizing damage, repairing it, and/or sealing the pores. Solutions here, along with reducing or eliminating the intermediate etch stops, are critical to a successful realization of the benefits from the use of lower-k materials. The surface preparation tables contain extensive updates on front-surface, back-surface, and edge-bevel defects, along with specifications on metallic contamination.

There has been a great deal of debate over reducing the edge exclusion on wafers from the current 2mm specification to 1mm, but the current measurement carries forward in the 2004 update. Surface preparation is one area of the Roadmap where the transition to the next wafer size is of critical importance. The next wafer size introduction, potentially 450mm, has been pulled in by one year to 2014 to match the timing in the Roadmap’s Front End Processing chapter.

Wet cleaning, plasma cleaning, and other dry cleaning methods - such as supercritical fluids and cryogenic aerosols - are all within the scope of surface preparation requirements. DRAM manufacturers are expected to address new surface preparation challenges as they move to Cu wiring, similar to what logic IC manufacturers did earlier in their migration to copper processes. An additional critical challenge will be to reduce roughness in the wiring, a potential way to mitigate the increase in copper resistivity by reducing surface scattering.

It is widely conceded that technology solutions alone cannot address challenges around the dielectric and wiring roadmaps in the short term, and perhaps not over the long-term 15-year horizon. Interconnect delay problems will be addressed by a combination of circuit design enhancements, innovative packaging approaches, and traditional scaling.

Christopher Case is chair of the ITRS Interconnect working group and CTO at BOC Edwards, Murray Hill, NJ; e-mail [email protected].

Click here to download Select updated near-term MPU interconnect technology requirements table.

Transistor scaling progresses, but new challenges loom

The Process Integration, Devices, and Structures chapter of the 2004 ITRS update [1] mostly contains only minor changes, corrections, and clarifications to the 2003 version [2]. The pace of transistor scaling and projected performance gains in CMOS logic remain on track, as expected. With an extensive re-evaluation and update planned for ITRS 2005, requirements for innovations in transistor scaling and alternatives for nonclassical CMOS structures will be scrutinized in the coming year.

Transistor scaling in the current ITRS is model-based with projected improvements in the transistor delay (τ) for high-performance logic set at 17%/year, the historical rate. For low-power logic, typically for mobile applications where low leakage is required to conserve battery power, the 2003 ITRS projected specific, low levels of source/drain subthreshold leakage current (Isd,leak) with scaling. In the 2004 update, projections are unchanged. The scaling of τ and Isd,leak is detailed for high-performance logic and for the two types of low-power logic: low operating power (LOP) and low standby power (LSTP). In the 2005 ITRS, transistor scaling will be re-evaluated and updated, but the general scaling trends are expected to be relatively unchanged, although presumably there will be adjustments in the specific numbers. In particular, the 17%/year improvement in the transistor delay for high-performance logic is expected to be maintained. Also, the scaling will be extended for two more years, to 2020.

As transistor scaling proceeds, it is expected to become increasingly difficult to fabricate transistors that meet Roadmap requirements - i.e., Isd,leak and τ projections, adequate control of short-channel effects, adequate control of statistical variation of transistor parameters, adequate reliability, and others. To meet these requirements, it is expected that numerous technology innovations (referred to as “potential solutions”) will be needed. In the 2004 update, the timing of key transistor potential solutions remains unchanged from the 2003 ITRS. A re-evaluation of these solutions and their timing will be carried out for the 2005 ITRS.

Enhanced mobility channels (through the utilization of strain) were introduced in 2004 and are expected to be commonly utilized in succeeding years. The next potential solution - high-k gate dielectric for low-power logic in 2006 - is needed to reduce gate leakage current as the thickness of the silicon oxynitride gate dielectric is reduced with scaling. This need is particularly acute for low-power logic because it requires very low leakage current. For high-performance logic, high-k gate dielectrics and metal-gate electrodes are projected to be needed in 2007. (Metal-gate electrodes would remove depletion inherent with polysilicon gate electrodes.) These innovations would allow the dielectric’s EOT to be scaled to below 1.0nm with acceptable levels of gate leakage current, as required for highly scaled high-performance logic transistors in 2007 and beyond. However, the re-evaluation of these latter potential solutions for the 2005 ITRS is not expected to lead to major changes.

The remaining potential solutions involve implementation of nonclassical CMOS structures, including ultrathin body, fully depleted, SOI single-gate MOSFETs with metal-gate electrodes, and subsequently, multiple-gate MOSFETs (which include the FinFET). The multiple-gate MOSFET also has an ultrathin body and is fully depleted, with metal-gate electrodes. The single-gate SOI MOSFET is projected to be required in 2008, while the multiple-gate MOSFET is projected to be required in 2010. In 2008, the MOSFET gate length is expected to be 22nm. For such highly scaled transistors, it will become very challenging for planar bulk MOSFETs to meet the requirements, even with utilization of enhanced mobility channel, high-k gate dielectric, and metal-gate electrodes. Achieving adequate control of short-channel effects will be especially difficult and will require very high channel doping. This high doping results in reduced mobility, increased junction leakage, and other deleterious effects. Furthermore, the total number of dopants in the channel becomes relatively small for these scaled devices, which leads to large statistical variations in the threshold voltage (Vt).

Nonclassical CMOS devices alleviate these problems. Since they are fully depleted, they can be lightly doped and Vt can be controlled by the work function of the metal-gate electrode, potentially reducing the statistical variation of Vt. Furthermore, the control of short-channel effects is inherently better in nonclassical CMOS devices than in planar bulk MOSFETs. Multiple-gate MOSFETs have the best short-channel effect control, and single-gate SOI MOSFETs are intermediate between multiple-gate MOSFETs and planar bulk MOSFETs. Therefore, the multiple-gate MOSFET, with various enhancements, is expected to be the ultimate scaled MOSFET.

References

Semiconductor Industry Association (SIA), International Roadmap for Semiconductors 2004 edition, Austin, TX, Sematech (http://public.itrs.net).
SIA, International Roadmap for Semiconductors 2003 edition, Austin, TX, International Sematech (http://public.itrs.net).
P. Zeitzoff, J. Hutchby, G. Bersuker, H. Huff, “IC Technologies: From Conventional CMOS to the Nanoscale Era,” Nano and Giga Challenges in Microelectronics, Eds. J. Greer, A. Korkin, J. Labanowski, Elsevier, pp. 1-25, 2003.

Peter M. Zeitzoff is chair of the ITRS Process Integration, Devices, and Structures working group and a Senior Fellow at Sematech, Austin, TX; ph 512/356-3608, e-mail [email protected].

Why wafer cleaning becomes more challenging

In the 2004 update of the ITRS, many targeted milestones for wafer cleaning remain unchanged from the previous year, but near-term and long-term requirements will undergo greater scrutiny during the drafting of the 2005 ITRS.

Figure. Potential solutions for interconnect surface preparation.Click here to enlarge image

Requirements for front-end-of-line (FEOL) surface preparation are being driven by both device scaling and new materials introduction. Device scaling is closing the process window in which cleaning efficiency is balanced with surface etching and pattern damage. Removal of particle contaminants requires either chemical reaction (bond-breaking) or physical force to overcome adhesion forces. The challenge is to supply enough chemical reaction or physical force to remove contaminants without removing excessive Si from the source and drain or SiO2 from the isolation trench, without adding excessive surface roughness, and without damaging patterned features such as the narrow gate electrode.

In the interconnect segment, stripping and cleaning processes are known to have a detrimental effect on the dielectric constant of low-k films in the insulating layers. Current etch and strip methods can damage new porous low-k films by removal of the carbon species. After subsequent wet cleans, critical dimension changes may be significant. Many dry methods of cleaning as well as new rinsing and drying techniques require more work (see Figure).

In FEOL surface preparation, many different approaches are under investigation to meet this challenge, including improvements to traditional batch wet-cleaning approaches, development of new single-wafer wet-cleaning approaches, application of gaseous aerosol approaches, and the use of supercritical fluids. Solutions appear to be identified for the 65nm technology node, but it is not clear yet whether current approaches can meet the 45nm technology node material-loss restrictions and still achieve sufficient cleaning efficiency to meet defectivity requirements.

The introduction of high-k materials has presented a challenge to surface preparation both in predeposition cleaning and in the need to remove high-k dielectric films from source and drain regions after formation of the gate electrode. High-k gate dielectric material is deposited on top of the silicon surface, whereas silicon oxide gate dielectric is formed by oxidizing the silicon surface. Because the high-k material is deposited, predeposition cleaning and surface preparation must be carefully controlled. Standard cleaning processes can easily leave a surface either oxide-free or with a 10Å layer of oxide. Ideally, one would like a very thin oxide layer of 2-5Å on the surface before high-k deposition. Processes to meet this challenge are under development. The removal of high-k material after gate electrode formation must be carried out with high selectivity to the gate electrode, to the isolation dielectric, and to the underlying silicon. Standard cleaning processes are not able to achieve the required selectivity. It appears that a combination of dry and wet processes will be required to meet the needs of this selective removal process and are under development.

Jeffery W. Butterbaugh is co-chair of the ITRS Frontend Processing working group and chief technologist at FSI International.

Christopher Case is chair of the ITRS Interconnect working group and CTO at BOC Edwards, Murray Hill, NJ; e-mail [email protected].

Editor’s Note: Tables and figures from the ITRS are courtesy of the SIA, The International Technology Roadmap for Semiconductors, 2004 edition, Sematech: Austin, TX, 2004.

Reading the 2004 update tables

The tables’ colored boxes should be interpreted as: white = solutions exist; yellow = solutions are known and being pursued; and red = no known solution. These tables may be slightly truncated from the official versions and are correct as of press time. The complete 2004 ITRS and tables are available for viewing and printing at http://public.itrs.net.