Results from SRTF show promise for shallow junction ion implant anneal
12/01/2002
overview
Thermal physics and process results in this study suggest that furnace-oriented implant anneal makes junction depth control easier and provides a wider process window than state-of-the-art spike anneal. Longer annealing at slightly lower temperatures than the current spike anneal process is a practical strategy for shallow as well as deep junction formation.
The objective of spike annealing used for shallow junction formation is to achieve maximum electrical activation with minimal dopant diffusion. The technique electrically activates implanted species with minimal thermal diffusion by heating a wafer very rapidly, and cooling it as soon as a target temperature is reached. Because this process requires a lot of electrical energy (250–350kW at peak) to achieve a fast wafer temperature ramp up (~250°C/sec), it is impractical for mass production.
As the demands of operational flexibility increase and the allowable thermal budget of devices decreases, single-wafer thermal processing becomes the preferred approach [1–3]. Rapid thermal processing (RTP) is widely used in device manufacturing today with lamp-based, single-wafer processing RTP systems and susceptor-based RTP systems having been introduced [4–5].
The lamp-based RTP system is equipped with sophisticated temperature measurement/control systems and requires a large amount of electricity during processing because of its poor energy efficiency. For shallow junction implant annealing applications, precise thermal management is essential for maximum electrical activation with minimum junction depth variation.
 Figure 1. Schematic diagram of an individual process module (furnace). |
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The wafer temperature control flexibility provided has long been believed to be ideal for precise thermal management. The sophisticated temperature measurement/control mechanisms and algorithms often cause repeatability problems, however, as well as lamp degradation and failure. The susceptor-based RTP system has higher energy efficiency, but its process application is limited to simple annealing processes in a low-pressure inert gas ambient due to the oxidation characteristics of susceptor material at high temperatures [5].
To improve process repeatability while operating at higher energy efficiency and productivity, a single-wafer rapid thermal furnace (SRTF) for RTP applications has been designed [6]. The system is capable of dry and wet rapid thermal oxidation (RTO) application [7]. In this paper, the design concept and thermal behavior of a dual chamber SRTF system are briefly described. Shallow and deep junction implant annealing were studied using the SRTF system. Sheet resistance and junction depth of implanted wafers after annealing were characterized as a function of annealing temperature and time.
 Figure 2. Typical wafer temperature profile during process. |
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SRTF system
The SRTF system has two vertically stacked process modules (furnaces) attached to one side of the wafer transport module. The stack of a vacuum loadlock and two cooling stations are attached to the other side of the wafer transport module to reduce the footprint. A cross-section of an SRTF process module is shown in Fig. 1. The process tube has three standoffs made of quartz and no moving parts inside. An R-type (Pt - 13% Rh/Pt) thermocouple is embedded in one of the quartz standoffs to monitor idle process environment temperature and wafer temperature during processing. The wafer is placed on the quartz standoffs (8–9mm tall) in the middle of the quartz process tube. The distance between wafer and both the top and bottom quartz walls is kept at ~10mm. The quartz process tube is located in a rectangular SiC cavity, which acts as a heat distributor to create an isothermal process environment. The SiC cavity is surrounded by a three-zone heater assembly.
The entire process module unit (quartz process tube, SiC cavity and heater assembly) is enclosed inside an aluminum chamber. The temperature of the SiC cavity is monitored by three embedded
R-type thermocouples and controlled by the three-zone heater assembly using feedback signals from the thermocouples to provide an identical and nearly isothermal environment for wafers regardless of wafer type and condition. The SRTF controls the SiC cavity steady-state temperature instead of wafer temperature. Also, instead of controlling wafer temperature directly, wafers are moved in and out of the preheated process tube. The process tube is made of quartz, has no moving parts, and provides a nearly particle-free process environment. It can be used in oxidation as well as annealing applications. The system is vacuum- and atmospheric pressure-compatible.
 Figure 3. Temperature sensitivity of sheet resistance of an implanted wafer after annealing. |
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Wafer temperature profile
Thermal behavior and process performance of the system are investigated in the temperature range of 200–1150°C. Temperature uniformity within the furnace is excellent — the color within the process area is very uniform. The wafer is introduced into a heated furnace and kept in the furnace for the entire process time, then removed from the furnace and heated as soon as it is introduced into the preheated furnace where its temperature increases rapidly and approaches the furnace temperature. The initial ramp rate is around 150°C/sec at a furnace temperature of 1100°C. When the wafer is quickly removed after processing, an exponential ramp-down is observed.
Measurements were made under 1atm-air using a thermocouple embedded instrumentation wafer during processing at different SiC cavity (furnace) temperatures; Fig. 2 summarizes the results. Since the process tube is surrounded by the heated SiC cavity, its temperature is almost identical to it. In an SRTF system, temperature overshoot is simply not possible because the furnace temperature is kept constant at process temperature. Process time, as referenced in a lamp-based RTP system, is the soak time near process temperature regardless of overhead times such as preheating, ramp-up and ramp-down times. Process time referenced in SRTF is the wafer residence time (from wafer-in to wafer-out) in a heated furnace.
 Figure 4. Sheet resistance (Rs) uniformity of an implanted wafer after annealing. |
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Implant anneal
Silicon wafers (200mm) implanted with various species (11B+, 49BF2+, 31P+, 75As+) at different implant energies (3–70keV) were annealed in the temperature range of 900–1100°C using the SRTF system. Annealing time (wafer residence time in the furnace) was varied between 35 and 180 sec. Since the annealing time includes the ramp-up time (~30 sec in the temperature range of 900–1150°C) and soak time, equivalent annealing time for the SRTF can easily be estimated by adding 30 sec to the soak time used in lamp-based RTP systems.
The effect of implant energy on process results was investigated in terms of annealing temperature and time sensitivity of sheet resistance after annealing. Sheet resistance and its uniformity were measured using a four-point probe after annealing. The junction depth of low-energy implanted wafers was determined by secondary ion mass spectroscopy (SIMS) after annealing using the SRTF and conventional lamp-based RTP system. Junction depth and sheet resistance of annealed wafers were compared. A new and practical implant annealing strategy for ultrashallow-junction formation was proposed based on theoretical considerations and experimental results.
 Figure 5. Annealing temperature and time-dependence of sheet resistance of implanted wafers after annealing. |
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50–70keV implant
Figure 3 shows the temperature sensitivity of sheet resistance of various types of deep implant wafers (11B+ 50keV 1 ¥ 1015/cm2, 49BF2+ 70keV 1 ¥ 1015/cm2, 31P+ 70keV 1 ¥ 1015/cm2 and 75As+ 70keV 1 ¥ 1015/cm2) after annealing. Annealing time was fixed at 40 sec. The sheet resistance of 11B+ and 49BF2+ implanted wafers dramatically decreases as the annealing temperature increases from 900 to 1000°C. Above 1000°C, a 11B+ implanted wafer continues to decrease its sheet resistance at a reduced rate, while a 49BF2+ implanted wafer slightly increases its sheet resistance due to the diffusion of boron atoms during annealing.
In contrast, 31P+ and 75As+ implanted wafers showed only slight decreases in their sheet resistance values even at higher temperatures. The wafers showed very little temperature sensitivity in the range 900–1100°C.
Figure 4 shows sheet resistance uniformity of various types of implant wafers after annealing in the temperature range 1000–1100°C, for 35 sec under 1atm-N2 atmosphere. The sheet resistance and its uniformity were comparable to, or better than, lamp-based RTP systems and comparable to ones obtained in conventional batch furnaces at a much faster cycle time. The process time (or cycle time) in SRTF is equivalent to, or better than, lamp-based RTP systems and is orders of magnitude shorter than that in conventional batch furnaces.
 Figure 6. Annealing temperature and time-dependence of sheet resistance of implanted wafers after annealing. |
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20keV implant
75As+ implanted wafers were annealed in the temperature range 900–1000°C in 50°C increments. Implant energy and dose amount were 20keV and 1 ¥ 1016 cm-2, respectively; annealing time was varied between 40 and 120 sec. The annealing temperature and time dependence of sheet resistance of implanted wafers after annealing are shown in Fig. 5. Unlike 70keV 75As+ implanted wafers, temperature sensitivity of sheet resistance is significantly higher. As annealing temperature and time increase, sheet resistance becomes lower. The sheet resistance value obtained by annealing for a short time at higher temperature can be matched by a longer anneal at lower temperatures.
It is well-known that Si diffusivity of atoms in Si increases exponentially as annealing temperature increases. Also, an increase in junction depth xj is proportional to the square root of annealing time in the case of an infinite source on the surface. To achieve maximum electrical activation with minimum dopant redistribution/diffusion, the implant anneal must be performed at an optimum (not necessarily higher) temperature for a reasonable amount of time.
The long-time furnace anneal at lower temperatures has been used for many years. If this furnace-oriented implant anneal process is used in a single-wafer RTP system, system productivity would be decreased significantly. Many RTP system providers and device manufacturers are focusing on development of short-time anneals at higher temperatures by varying wafer temperature ramp-up/down rates, such as in a spike anneal.
 Figure 7. SIMS depth profiles of As atoms after annealing at different conditions. |
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3keV implant
Low-energy ion implanted (75As+ 3keV, 2 ¥ 1015 cm-2) wafers were annealed using the SRTF system under various conditions. For comparison, a lamp-based RTP system was also used. Figure 6 shows the sheet resistance of implanted wafers after using both methods. The sheet resistance values for the wafers annealed using the lamp-based RTP system at 1000°C, 1 sec (spike anneal) and 950°C, 10 sec (soak anneal) are indicated as solid lines. As seen in the figure, the sheet resistance value can be adjusted by selecting the appropriate annealing temperature and time in the SRTF system. Lower sheet resistance values were achieved in wafers annealed using the SRTF system.
Figure 7 shows SIMS depth profiles of As atoms in implant wafers annealed at different conditions. The wafer annealed at 950°C for 50 sec in the SRTF system has a reasonable sheet resistance value of 423.8 W/sq. and the least amount of dopant redistribution in the depth direction. A junction depth of 21nm (at 1 ¥ 1018 cm-3) was obtained in a 75As+ (3keV, 2 ¥ 1015 cm-2) implanted wafer after annealing at 950°C for 50 sec in the SRTF system.
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The wafer annealed at 950°C for 10 sec in the lamp-based RTP system resulted in a sheet resistance value of 414.4 W/sq. and junction depth of 23nm (at 1 ¥ 1018 cm-3). For the spike annealed wafer at 1000°C, sheet resistance and junction depth were 477.8 W/sq. and 29nm, respectively. Both wafers annealed at 950°C showed similar dopant depth profiles and lower sheet resistance compared to the spike annealed wafer at 1000°C.
From the device fabrication point of view, the higher surface dopant concentration observed in the wafers annealed at 950°C can be beneficial for reducing contact resistance. The sheet resistance can be lowered further by increasing annealing temperature and time in the SRTF system. The wafers annealed at 1000°C there can also be useful for the bulk sheet resistance reduction as long as the dopant diffusion level is acceptable. Relatively longer annealing (30–180 sec) at slightly lower temperatures from the spike anneal temperature would be ideal for a new, practical implant annealing strategy for shallow junction formation.
This study strongly suggests that the spike anneal, which is currently widely used for shallow junction implant anneal, needs to be re-evaluated from the thermal physics and device physics point of view.
Productivity
Very high wafer throughput is achieved due to the stacked dual furnace configuration and efficient temperature ramp-up/down characteristics of the SRTF system. Throughputs of ~60 wafers/hr can be achieved for 60 sec processes with a 60 sec cool-down step. Average steady state power consumption at 1150°C is <3.5kW/furnace. Since the SiC cavity temperature is controlled at steady state, the peak power requirement does not normally exceed twice the average steady-state power consumption. Lamp-based RTP systems typically consume a peak power of 50–250kW/.process chamber to heat a 200mm wafer to 1000°C at a reasonable ramp rate (50–250°C/sec). The SRTF system provides high-quality results and process flexibility at reasonable throughput (~30 wph/process chamber for a 60 sec process) and high energy efficiency (<3.5kW/process chamber at 1100°C).
The system can operate under vacuum/atmospheric pressure, and a variety of process applications, including annealing and oxidation, are possible in the 200–1150°C temperature range . Typical process applications include metal silicidation (TiSi, CoSi, NiSi, WSi etc.), dry/wet oxidation, and glass film reflow.
Conclusion
The concept and feasibility of a vacuum- and atmospheric pressure-compatible, stacked dual-furnace SRTF system were demonstrated. The wafer temperature profile including ramp-up and ramp-down characteristics were characterized as a function of heat source temperature and processing time. Silicon wafers implanted with various species at different implant energies were annealed. Excellent process uniformity (<1.0% in 1s) and appropriate sheet resistance were obtained in implanted wafers after annealing, regardless of implant species.
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Relatively longer annealing at slightly lower temperatures than the spike anneal temperature was proposed as a new, practical implant annealing strategy for shallow junction formation. A junction depth of 21nm (at 1 ¥ 1018 cm-3) was obtained in an 75As+ (3keV, 2 ¥ 1015 cm-2) implanted wafer after annealing at 950°C for 50 sec in the SRTF system. Longer annealing at slightly lower temperatures from the current spike anneal process is a practical strategy for shallow junction formation.
The effectiveness of spike annealing was questioned, based on the thermal physics of electrical activation and diffusion of implant species. Electrical activation starts at lower temperatures (800–900°C) and saturates with time. The diffusion speed increases exponentially as annealing temperature increases. To electrically activate implanted species efficiently with minimum diffusion, relatively longer annealing at slightly lower temperatures than the spike anneal temperature would be ideal. This strongly suggests that the spike anneal, currently widely used for shallow-junction implants, needs to be re-evaluated.
References
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Woo Sik Yoo received his BS in electronic engineering from Dongguk University in Korea, MS and PhD degrees in electrical engineering from Kyoto University, and an MBA degree from Western Connecticut State University. He is chief technical officer of WaferMasters Inc., 246 East Gish Road, San Jose, CA 95112; ph 408/451-0856, fax 408/451-9729, [email protected].
Takashi Fukada received BS and MS degrees in electrical engineering from Kyoto Institute of Technology, Japan. He joined WaferMasters in 1999 and is responsible for process engineering activities.
Riu Komatsubara is a graduate of Tokyo Metropolitan Air Industrial College and Tokyo Denki University. He has more than 20 years of experience in the semiconductor equipment business at Tokyo Electron Ltd. and is general manager of the company's Thin Film & Cleaning Group.
Jiro Yamamoto received his BS in electrical engineering from the University of Mie in Japan. He joined NEC Corp. upon graduation and is currently senior manager of production engineering at Hiroshima NEC Ltd.
Woo Sik Yoo, Takashi Fukada, WaferMasters Inc., San Jose, California Riu Komatsubara, Tokyo Electron Ltd., Jiro Yamamoto, NEC Corp.