Using phase shifting to extend 248nm litho beyond the 50nm gate process
11/01/2002
Using phase shifting to extend 248nm litho beyond the 50nm gate process
By C.Y. Fang, K.C. Hung, Z.X. Huang, S.H. Hsu, UMC, Hsinchu, Taiwan J. Huang, Numerical Technologies Inc., San Jose, California
overview
Using a dark-field AltPSM double-exposure process, it is possible to print gates at 50nm. By optimizing some key parameters, 248nm and 193nm lithography can be used to print gates as small as 25nm [1].
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Reticle-based resolution-enhancement techniques (RETs) have proven to be the main driving force enabling the patterning of sub-100nm semiconductor devices. By implementing techniques such as phase-shift masks (PSMs), optical proximity correction (OPC), and off-axis illumination, IC manufacturers can achieve robust subwavelength imaging performance well beyond conventional resolution limits.
At the same time, existing technology challenges and the ongoing 193nm lithography delay have necessitated extension of 248nm-based lithography far beyond what the industry had originally anticipated. Currently, a double-exposure-based, dark-field, alternating PSM (AltPSM) technology is the only mature technology that has been proven able to meet the tight critical dimension (CD) control requirement for high-performance CPUs and GPUs [2–4]. Previous work conducted at MIT Lincoln Labs illustrated its effectiveness in extending 248nm lithography for the manufacture of transistors with gate lengths as small as 25nm [1].
To begin, 300Å of optimized silicon oxynitride (SiON) was deposited on poly film to suppress standing waves and provide good control of substrate reflectivity. After-development inspection (ADI) showed that the CD deviated by 5nm. The ADI CD parameters were defined by double-exposure technology with a dark-field AltPSM and a binary trim mask. Figure 1 illustrates how double-exposure layout features, such as regulator width, shifter width, and shifter height, are defined. Mask CDs for binary and AltPSM exposures were 160nm and 110nm, respectively, while related ADI CD targets were 130nm for the binary mask and 80nm for the AltPSM. Resist trimming was performed after development, and the gate was then shrunk to 50nm. All pitches, from dense to isolated, were necessary to meet the depth-of-focus (DOF) requirement.
To accommodate the trim-based process, a positive deep-ultraviolet (DUV) resist with high activation energy was used — Mxx from Tokyo Ohka Kogyo Co. (TOK). Resist thickness was determined by the aspect ratio of ADI thickness to ADI CD; an aspect ratio of 4 is necessary to prevent resist collapse, particularly if nested lines are present.
Finally, the wafers were exposed on a Nikon S204 scanner with an AltPSM and a binary mask, and then developed in a 2.38% surfactant. CDs were measured on a KLA-8100 top-down scanning electron microscope (SEM), while KLA-Tencor's PROLITH 7.0 lithography simulation software and Numerical Technologies' IC Workbench process-performance analysis tool were used to obtain simulation results.
 Figure 1. Definition of double-exposure layout features. |
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Baseline results for 50nm gate formation
Baseline process performance results confirmed that 248nm lithography can be extended for the 90nm node by using AltPSM technology. Figure 2 shows the top-down CD-SEM images of nested patterns with a CD target of 80nm and different pitches from 240–1200nm. All results showed good printability and small line-edge roughness. In Fig. 3, line cross-sections in photoresist are shown to have straight profiles used with a range of different shifter widths and pitches. After-etch poly gates, with CDs targeting 50nm, featured consistent through-pitch performance.
CD uniformity was monitored using electrical CD metrology based on a test pattern with an isolated feature. The sampling size used was 14 measurement sites/field, and 50 fields/wafer under optimal exposure conditions. Inter-field CD variation 3s results were 5.3nm, 5.4nm, and 4.5nm for ADI, after-trim inspection (ATI), and after-etch inspection (AEI), respectively.
Compared to CD uniformity for a conventional binary mask (BIM), AltPSM technology exhibited significantly better performance. Intra-field CD uniformity for AltPSM was also excellent — 3s ADI and AEI CDs were 4.7nm and 4.6nm, respectively, based on results obtained from 14 cross-field measurement sites (see the table). While these results were both compelling and impressive, further experimentation proved that process performance could be enhanced even further by optimizing critical layout parameters, optical settings, and the photoresist process.
 Figure 2. Top-down CD-SEM images of through-pitch lines with an isolated CD target of 80nm (pre-OPC regulator width = 110nm, 0.64 NA/0.42s, shifter width = 500nm). |
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Optimizing phase-shifter width
PSM pattern properties, like the regulator and phase-shifter dimensions, must be tuned along with optical settings to achieve optimal process performance. Phase-shifter width has a strong effect on printed-gate CD (Fig. 1). As shifter widths increase from 250 to 500nm, printed CDs enlarge by about 20–25nm, while shifter widths larger than 500nm do not significantly affect the printed line width. Thus, the shifter width was used as the key factor for optimizing through-pitch proximity bias. The proximity bias for 305nm and 500nm shifter widths was 27nm and 7nm, respectively, for pitches greater than 600nm (Fig. 4). This result was obtained for a regulator width of 110nm and 0.64 NA/0.42s optical settings (NA = numerical aperture).
By examining exposure latitude (EL) performance versus DOF, one can understand how phase-shifter width affects the process window. Results from research indicate that the EL/DOF process window becomes significantly larger with the increase of shifter width; thus, optimal imaging performance can be achieved with a phase-shifter width of 500nm. This optimized shifter width minimizes proximity bias while improving the process window.
Shifter-width optimization requires a trade-off in the PSM design. While larger shifter widths significantly improve lithographic process performance, they also put more constraints on phase-conflict resolution. A trade-off can be achieved by selecting a minimum shifter width with adequate process performance that uses multirules.
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Optimizing optical settings
As with PSM parameters, optical settings must be optimized to achieve the best possible process performance. Initial optimization was performed based on simulations in IC Workbench. The EL/DOF process window is improved by using lower partial coherence. Although a smaller NA setting helps to enhance DOF, it must be moderately large to resolve dense lines with sufficient image contrast. Unlike isolated patterns, the resolution of dense lines is limited by the optical k1 factor value of 0.25. Results shown in Fig. 5 illustrate the EL/DOF process-window performance for multiple pairs of NA-partial coherence settings.
Tuning chrome regulator size
While chrome regulator size does not have a significant effect on CD sensitivity to shifter width, through-pitch process-window results indicate that a smaller chrome regulator helps to enlarge both exposure latitude and depth of focus, especially in the case of isolated lines. Chrome regulator size was optimized through simulations. Using IC Workbench, process windows were simulated for regulator sizes of 100nm, 120nm, and 150nm, using an optimized shifter width of 500nm and optical conditions of 0.64 NA and 0.42s.
The results indicated a decrease in DOF with pitch reduced to 320nm, but as regulator size increased, this trend became less distinct, especially for pitches smaller than 400nm, where EL/DOF curves appear practically overlapped. As the OPC process employs regulator width as a variable to reduce proximity effects, post-OPC minimum DOF pitch may no longer be the smallest pitch. Figure 6 shows post-OPC through-pitch process-window performance using 0.64 NA/0.42s optical settings. The results indicate that minimum DOF and exposure latitude are achieved at 380nm pitch.
 Figure 4. An example showing through-pitch CD dependence on shifter width. |
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Improving DOF through photoresist process optimization
Through-focus CD uniformity at the forbidden pitch can be improved by increasing the diffusion length.
Simulation results showed improvement in through-focus CD uniformity with the increase of diffusion length, while an increase in post-exposure bake (PEB) temperature resulted in better through-focus CD uniformity.
Through-pitch proximity bias did not show significant sensitivity to the change of soft-bake (SB) and PEB temperatures for dense lines with pitches up to 400nm (Fig. 7). However, a small proximity-bias reduction can be observed for line-width pitches of 400nm and larger as the PEB temperature increases from 110–120°. An increase in PEB temperature had a positive impact on process latitude. Results showed that the experimental DOF at the forbidden pitch of 380nm improved by more than 25% at 8% exposure latitude as a result of increased PEB temperature.
 Figure 5. Simulation of nested-line EL/DOF process windows vs. various NA/s optical settings. |
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Conclusion
With next-generation lithography technology still as much as seven years away from fruition, the industry has increasingly turned to subwavelength technologies such as PSM and OPC to extend existing lithography techniques. As the baseline process described illustrates, extending 248nm lithography for use in 100nm technology-node manufacturing, patterning gates down to 50nm or even smaller can be achieved using a dark-field AltPSM double-exposure process.
 Figure 6. Post-OPC through-pitch process windows. |
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In addition to consistent through-pitch imaging performance, initial results from the work summarized showed that the common process-window size was limited primarily by line density. CD uniformity was tested electrically, showing inter- and intra-field 3s of <6nm for AltPSM. Finally, optimizing various critical process parameters improved process performance, helping increase the applicability of this PSM approach to extending 248nm lithography much further than even the technology's originators could have foreseen.
 Figure 7. Impact of SB and PEB temperatures on through-pitch CD proximity. |
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Acknowledgments
Additional authors of this article include P.W. Yen and J.R. Huang of UMC, and H.Y. Liu of Numerical Technologies Inc.
References
1.M. Fritze et. al., "Application of Chrome-less Phase-shift Masks to sub-100nm SOI CMOS Transistor Fabrication," Proc. SPIE, Vol. 4000, p. 338, 2000.
2.G.P. Watson et. al., "A 2-million Transistor Signal Processor with 120nm Gates fabricated by 248nm Wavelength Phase-shift Technology," MNE '99.
3.M.E. Kling et. al., "Practical Extension of 248nm DUV Optical Lithography Using Trim-mask PSM," Proc. SPIE, Vol. 3679, pp. 10–17, 1999.
4.C.M. Wang et al., "Patterning 80nm Gates Using 248nm Lithography: An Approach for 0.13µm VLSI Manufacturing," Proc. SPIE, Vol. 4346, pp. 425–463, 2001.
Cheng Yu Fang received his master's degree from National Chiao Tung University, Taiwan. He is a principal engineer, Advanced Module A Department, Central R&D Division, at UMC.
Kuei Chun Hung received his master's degree from National Taiwan University. He is department manager, Advanced Module A Department, Central R&D Division at UMC. UMC, No.3, Li-Hsin Rd. II, Science-Based Industrial Park, Hsinchu City, Taiwan 30077; ph 886/3-578-9158 ext. 32007, e-mail [email protected].
Zhi Xian Huang received his master's degree from National Chiao Tung University, Taiwan. He is a principal engineer, Advanced Module A Department, Central R&D Division, at UMC.
Shu-Hao Hsu, received his master's degree from National Cheng Kung University, Taiwan. He is a principal engineer, Advanced Module A Department, Central R&D Division, at UMC.
Jason Huang received his master's degree in chemical engineering from National Cheng Kung University, Taiwan, and has been a process and R&D manager at PSMC. He is director of technology and lithography applications at Numerical Technologies Inc., 70 West Plumeria Drive, San Jose, CA 95134; ph 408/919-1910, e-mail [email protected].