Slurryless CMP enables next-generation direct polish STI

11/01/2002

By Annabel Nickles, Dan Marohl, Gopal Prabhu, Tom Osterheld, Applied Materials Inc., Santa Clara, California

overview
As device geometries continue to shrink, planarity requirements for shallow trench isolation chemical mechanical planarization are becoming increasingly stringent. Additionally, cost pressures are driving more chip manufacturers to use direct polish STI CMP instead of the much more expensive and time-consuming reverse masking processes. Key process performance metrics for STI CMP are the post-polish trench oxide and active area nitride thicknesses, as well as the within-die and within-wafer thickness ranges for both of these.

Challenges in direct polish shallow trench isolation chemical mechanical planarization (STI CMP) arise from variations in layout feature sizes and densities. Within a single die, high-density areas tend to polish more slowly than low-density areas. By the time oxide is cleared from high-density areas, low-density regions are already overpolished and can suffer from excessive oxide dishing and nitride erosion, driving up within-die (WID) ranges. Typically, DRAM or other memory-style layouts are more uniformly dense and easier to process using direct polish STI CMP, whereas logic-style layouts, with wider variations in feature sizes and density, pose a greater challenge.

Figure 1. Comparison of dishing values for different direct polish STI CMP processes: silica slurry, ceria HSS, and fixed-abrasive web. All data were measured on wafers patterned with an MIT STI test mask (Sematech 964 wafers) on 100µm-pitch structures.Click here to enlarge image

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Achieving the required WID ranges for both trench oxide thickness and active area nitride thickness while minimizing overpolish into the nitride stop layer is driving development of advanced technologies for performing direct polish STI CMP. Trench oxide dishing and active area nitride erosion requirements for 100nm and below cannot be met using conventional silica slurry direct polish techniques.

A solution for next-generation direct polish STI is fixed-abrasive web CMP [1, 2]. This slurryless process utilizes a new CMP consumable in which all polishing abrasive is affixed to a backing sheet. Fixed-abrasive web CMP virtually eliminates oxide dishing and nitride erosion. This performance is demonstrated in a process that also has low defect levels, is applicable to a wide range of mask layouts, and has very good wafer-to-wafer (WTW) repeatability of results.

Figure 2. Trench (oxide) and nitride thickness measurements on a lot of 25 patterned DRAM STI test wafers showing a very large overpolish window. The first 12 wafers were polished just to the point of clearing all oxide. The last 13 wafers were polished for an additional 60 sec, or overpolished by ~100%.Click here to enlarge image

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Planarity performance

All of the experimental results presented in this paper were obtained on an Applied Materials' Reflexion fixed-abrasive web CMP system. Specialized web-magazines for handling fixed-abrasive material are substituted for individual rotary platens of the standard system. Any or all of the platens can be replaced with web-magazines.

Typically, with slurry CMP, free abrasive particles in low areas (trench) are subject to hydrodynamic forces and contribute to excessive dishing in these low regions. Compared to a standard silica slurry direct STI process, dishing in fixed-abrasive web CMP is lower by roughly a factor of ten. This is the result of the abrasive's confinement to the web material. Unlike slurry polishing, there are no abrasive particles free to polish low trench areas that are not in contact with the web surface.

Figure 3. 300mm wafer maps showing total defect adders. Using a) unoptimized conditions, defect adders are higher and clustered around the edge of the wafer. Using b) optimized conditions, defect adders are minimized. Defects were measured on a KLA-Tencor SP1 at 0.16µm.Click here to enlarge image

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More recently, ceria high-selectivity slurries (HSS) that exhibit non-Prestonian polishing behavior have been employed for direct STI CMP. (For non-Prestonian slurries, low polishing pressures, such as in hydrodynamically driven polishing, result in very low removal rates.) These slurries offer significant improvements in dishing over conventional silica slurries; however, fixed-abrasive web dishing is still 2–3¥ lower than that attainable using ceria HSS. Figure 1 on p. 59 compares dishing values for all three of these techniques. It is important to note that the relative dishing magnitudes hold for the entire range of densities measured, from 10–90%.

Without any polishing process modification, a fixed-abrasive web removes nitride as well as oxide. Once the oxide is cleared, continued polishing erodes away the nitride layer. WID nonuniformity and within-wafer nonuniformity are functions of overpolish and increase as the nitride loss increases. Nitride erosion is significantly reduced by the addition of selective chemistry to the polishing fluid. Amino acids like glycine and l-proline have both been shown to effectively lower the nitride removal rate in fixed-abrasive web polish [3]. Utilizing these types of chemistries, nitride erosion can be minimized, much as with ceria HSS. Unlike a ceria HSS process, however, oxide dishing is virtually eliminated at the same time.

With very low dishing and nitride erosion, polishing essentially stops when oxide is cleared at the end of the STI CMP step. This opens up a very wide overpolish window for most processes. Figure 2 shows results from a 25-wafer lot of DRAM test wafers polished with fixed-abrasive web using selective chemistry. The first 12 wafers are polished just to the point of clearing oxide, and the last 13 are overpolished by 60 sec, or about 100%. Neither trench nor nitride thickness was significantly altered by the 100% overpolish.

Figure 4. Trench (oxide) and nitride thickness measurements over a 25-wafer lot of patterned DRAM STI test wafers polished with Reflexion fixed-abrasive web CMP.Click here to enlarge image

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Defectivity

A major concern for the critical STI CMP step is defectivity. In particular, microscratches left on the active transistor area by the STI CMP step can cause significant yield loss and must be controlled to the lowest attainable levels. Most STI CMP production processes of record (POR) using conventional silica slurries have microscratch levels/wafer of 10 (single-digit range). In order for fixed-abrasive STI CMP to be widely adopted for manufacturing, defect levels must be at least no worse than current POR levels.

Microscratches in fixed-abrasive web CMP arise largely from particulates emanating from either the web material itself or from inclusions in fluid chemistries used on the web. Web materials are engineered to control ceria particle properties, including particle size and size distribution, so as to minimize the number of large particles that could produce microscratches. Particulates or inclusions in fluid chemistry can be controlled with point-of-use filtration (much as is done with silica slurry in conventional CMP; in this case, moreover, filtering fluid chemicals is much simpler than filtering slurry). By filtering fluid chemicals, the number of total defect adders is cut roughly in half.

Figure 5. Wafer diameter scans of trench (oxide) thickness measurements showing improvements made with new processes and materials on challenging logic-style layouts. Measurements were made on trenches 30–500µm in width, and on 10–70% densities. Newer processes and materials result in b) lower WID trench ranges than a) previously attainable. All measurements were made on wafers patterned with an MIT STI test mask (Sematech 964 wafers).Click here to enlarge image

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Eliminating large particles that can cause microscratches is critical to controlling defect levels, but other factors are also important. It has been found that wafer-handling and process conditions also impact defect and microscratch levels. Figure 3 shows two 300mm wafer maps with total defect adders, one polished with unoptimized process and wafer handling, the other with optimized conditions. Defect levels, especially at the wafer edge, are significantly reduced with optimized conditions. Comparing fixed-abrasive STI patterned-wafer microscratch levels with those from a silica slurry polish shows that fixed-abrasive microscratching is on a par with silica (single digit/wafer). Particle adder levels are easily controlled with standard cleaning techniques, including a megasonics bath step, in the system cleaner.

Wafer-to-wafer process repeatability

Web-magazine implementation of fixed-abrasive CMP results in very good WTW process repeatability. During polishing, the web material is held stationary on the magazine surface while both head and web-magazine rotate in the horizontal plane. Between wafers, the web is indexed, or incremented, by ~5mm. (For a two web-magazine polish sequence, the sum of the increments on magazine 1 and magazine 2 is ~10mm for 300mm wafers, and ~5mm for 200mm wafers.) Web material, therefore, is consistently being replenished for each wafer, or more simply stated, each wafer "sees" the same polishing surface. This results in excellent WTW process repeatability. Figure 4 shows typical fixed-abrasive web CMP results for direct polish STI on a 25-wafer lot of patterned DRAM test wafers. The standard deviation (1s) of trench WTW thickness values is <0.5%, and the nitride WTW 1s is <1%.

Flexibility

The earliest generations of STI web materials were developed to perform well on the very regular densities and small feature sizes characteristic of DRAM mask layouts. Newer materials have enabled process development for more challenging logic-style masks, those with wide density variations and feature sizes that can be up to several hundred microns. Figure 5 shows trench thickness measurements from two STI test wafers containing a wide array of feature sizes and densities. One was polished with the earlier web materials and processes targeted at DRAM masks, and the other with newer materials and processes developed for logic-style masks. As seen in the figure, the new processes are able to achieve a WID trench range of 300Å over trench sizes ranging from 30–500µm, and densities ranging from 10–70%.

Conclusion
As chip manufacturing progresses through 100nm generations and beyond, increasingly demanding planarity requirements for direct polish STI CMP necessitate advanced technologies. Planarity performance that virtually eliminates dishing (factor of 10 lower than silica slurry and 2–3 lower than ceria HSS) coupled with stop-on-nitride selectivity has been demonstrated using the Reflexion system. System architecture and choices of web materials enable process flexibility for tailoring polishing sequences. A web-magazine implementation enables direct STI CMP WTW repeatability, along with defect and microscratch levels that are equivalent to current POR levels.

Acknowledgments
The following colleagues from Applied Materials are co-authors of this article: Garlen Leung, Greg Menk, Vasanth Mohan, Pete McReynolds, and Eric Rondum. SlurryFree is a trademark of 3M. Reflexion is a trademark of Applied Materials Inc.

References
1.L. Economikos et al., "STI Planarization Using Fixed Abrasive Technology," Future Fab International, Issue 12, 2002.
2.J. Gagliardi, T. Buley, "3M SlurryFree CMP Fixed Abrasives for Direct HDP STI CMP," 3M Technical Brief, June 2001.
3.J. Gagliardi et al., "Fixed Abrasives and Selective Chemistries: Some Real Advantages for Direct STI CMP," Proc. 7th CMP-MIC Conf., pp. 274–281, March 2002.

Annabel Nickles received her BS in materials science from MIT in 1989, and her PhD in the same field in 1998 from the University of California, Berkeley. She has worked in the semiconductor industry as a process and integration engineer, and is currently a new product development manager for STI CMP applications at Applied Materials Inc., 3050 Bowers Ave., Santa Clara, CA 95054; ph 408/235-4322, e-mail [email protected].
Dan Marohl received his electrical engineering degree from DeVry Institute of Technology in 1990. He has worked in the semiconductor equipment industry in product support, system engineering, and product design engineering for 12 years. Marohl is an engineering manager of new product development at Applied Materials' CMP division.
Gopal Prabhu received his B.Tech in metallurgy in 1991 from the Banaras Hindu University in India. He received his PhD in materials science and engineering from the University of Texas at Austin in 1996, and has worked in the CMP Division at Applied Materials since then.
Tom Osterheld received his PhD in physical chemistry from Stanford University in 1992. For the past seven years, he has worked on CMP process and hardware development at Applied Materials. Osterheld is in charge of the STI CMP group.