Evolving business strategies are key to an upbeat 300mm outlook
10/01/2002
Regardless of the economic doldrums facing the industry in general, analysts looking at the status of 300mm see a fairly bright outlook. Semico Research Corp.'s latest report proclaims that the two conditions historically necessary for aggressive conversion to larger wafers — accessible technology and reasonable economics — are now in place [1]. The company believes that 300mm capacity will surge during the next two to three years, growing to 45% of total wafer production by 2006 (Fig. 1).
Even IC Insights acknowledges that in spite of some curtailment in the migration process because of the economic downturn, 300mm progress was not derailed [2]. Bill McClean, president, credits two main reasons why progress is still moving forward: 1) the increased difficulty of decreasing per-die costs with feature shrinks, and 2) IC manufacturers are using the downturn as an opportunity to mature their factory control systems and equipment. The report predicts about 32% of total worldwide silicon wafer area used will be in 300mm wafers by 2006 (Fig. 2).
The McClean report also presents data that make a case for the microprocessor segment driving the transition to 300mm. Complex, high-end logic devices (MPUs, DSPs, ASICs/FPGAs) can achieve per-die production cost savings much greater than for DRAMs (Fig. 3). For example, one source reports a relative cost of ~24 vs. ~9 for a 400mm2-die-area FPGA.
Analysts are continuously adjusting their forecasts to take into account unique conditions facing the industry, including sinking ASPs (average selling price) in the face of the typical 8%/yr growth in unit volume shipments (Fig. 4). China will probably not be the land of opportunity the industry has been banking on — for either 200mm or 300mm manufacturing, noted Dan Hutcheson, president of VLSI Research, at a Semi forecast session. He cited lagging-edge capacity in China while personal bankruptcies rise. McClean emphasizes the huge disconnect between what China needs for its own consumption, leading-edge consumer electronics, vs. what its fabs will be able to make — lagging-edge devices. The plan for China's fabs to target the foundry market does not seem likely to work, because fabless companies need leading-edge technology.
 Figure 1. Wafer size transition history, 19912006. (Source: Semico Research Corp.) |
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IDMs vs. foundries?
Until recent technology shifts to copper and low-k materials with their attendant integration challenges made it more difficult for foundries to stay on the cutting edge of process technology, some pure-play foundries took the lead, or at least were running neck and neck, with the large IDMs. But being a leader in 300mm manufacturing will not be as easy. Still, industry observers interviewed for this article had some diverse opinions on the topic.
Because foundries can aggregate multiple small pockets of demand, they will be able to justify adding 300mm capacity and do well in the next upturn, according to Mihir Parikh, chairman of Asyst Technologies. He points out, however, that right now there does not appear to be much demand that would justify adding capacity in the range of 15,000–20,000 300mm wafers/month, what he considers the break-even point.
 Figure 2. Semiconductor wafer size transitions. (MSI = millions of square inches; sources: Rose Associates/IC Insights Inc.) |
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"The real question is, when will the second tier of 300mm fabs make the transition from pilot lines to full production," states Parikh. "And then, when will additional second-tier players begin to build new 300mm fabs?" Not surprisingly, Parikh thinks the yield and productivity improvement gained via automation will play a key role in lowering the threshold of unit demand required to justify building a 300mm fab.
For Dongbu Electronics, just beginning its foray into 300mm manufacturing, quantity is not everything, but flexibility, the strong suit of the foundry sector, is. With ground already leveled for its new fab, the company expects to start 300mm manufacturing by the end of 2003. "Among the 300mm foundries that gain competitive advantage will be those that can profitably produce smaller wafer lots, or single-wafer lots, and not necessarily those that simply offer a large wafer capacity," states Aabid Husain, director of worldwide marketing at Dongbu.
Agreeing that the economic sense for migrating to 300mm wafers is to be realized only if volume is attained, Hans Stork, senior VP of process development at TI, believes that, unless the industry grows, greater consolidation is in store for the sector. "You need a large enough volume to balance demand fluctuation," comments Stork. He acknowledges that foundries will benefit from 300mm cost savings, "They are well set up to handle a large diversity of customers and loadings, and foundries have also invested in the IT infrastructure to handle such diversity."
Stork adds, however, that TI believes owning its own fabs will continue to provide advantages over fabless competitors. "The transition from 6 in. to 8 in. took its toll on the industry and the 8-in. to 12-in. transition will also take a toll," says Stork. "Only about six companies will be able to stay in leading-edge technology development — and 300mm is one technology milestone that will separate those companies from the rest."
UMC's Chris Chi, senior VP, also believes that the most important factor for 300mm cost reduction is to reach critical mass, i.e., achieving high volume above the break-even point. "A full 200mm fab will always be much more cost efficient than a partially full or smaller 300mm fab until the volume reaches a certain level," explains Chi (Fig. 5). "Volume also drives the learning curve to improve yield and reduce cost." Chi believes that a 300mm fab with economy of scale will cost around US$3 billion, although a 300mm pilot line that produces a minimum volume could be done for US$500 million.
One way to ease into 300mm territory is exemplified by Chartered Semiconductor. The company is working with 300mm now — developing equivalent processing techniques using equipment sets at vendor facilities for both customer development wafers and Chartered qualification vehicles for its own processes and tools. The company increased its 2002 capital expenditures from $400 million to $500 million, and has asked for earlier delivery of selected 300mm equipment. The first tools for the 300mm automation infrastructure at its all-copper Fab 7 are slated for installation later this year, and production is expected to begin by 3Q03, says John Martin, Chartered CTO.
Given the previously cited data on the microprocessor driving the migration to 300mm, it might be tempting to think that Intel would not need to do much more than make its own microprocessors, but such is not the case. Although the company has not had many announcements regarding its Microlectronics Services business (IME), the company believes it has achieved a win-win formula, — one that does not pit IDMs against foundries. Using Intel's own product, design, and test engineers, along with the relationships it already has with third-party IP vendors, foundries, and test/assembly/packaging houses, Intel's IME provides a completed ASIC/ASSP device with the only input needed being the RTL or netlist.
Fred Cohen, IME's director of marketing, explains that Intel's expertise is used to help a client make the right business decision, including how to optimize the process so as to reduce mask costs (see "Mask cost containment strategies" on p. 31), as well as whether or not 300mm manufacturing is cost-effective for a particular product or whether staying at 200mm makes better sense. Like other foundries, IME offers multidie shuttle services. About 60% of IME customers are system manufacturers, the remainder are application-specific standard part (ASSP) providers. The IME model seems to play into the predictions of industry analysts who say that collaboration and alliances will be key for survival of the smaller players who cannot afford to go down the 300mm road alone.
 Figure 3. 300mm wafer consumption by device type. Logic includes ASICs, MPUs, DSPs, etc. (2003 forecast, 480 MSI; source: IC Insights Inc.) |
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Wafers
Demand forecasts are predictions, not absolutes; thus, a challenge for 300mm manufacturing starts with wafers themselves. "I consider this [demand forecast reliability] to be one of the most challenging issues," says Volker Braetsch, VP, global marketing & business development, Wacker Siltronic. "It is complicated further that from 50+ companies having 200mm lines, you move to a handful (5–10) with 300mm lines short- and mid-term. The boom or bust of a single IC manufacturer can define the faith of even major silicon wafer makers."
A cautionary note comes from MEMC's John Kauffmann, director of marketing: "None of the semiconductor manufacturers are consuming a lot of 300mm wafers. Each is consuming between 5000–15,000 production wafers/month, so the market size is relatively small but will continue to grow in importance."
With most of the 300mm wafer demand for devices at the 130nm node and below, capacity of 300mm fabs at sub-100nm nodes is expected to be less than the volume levels of previous shrinks, says André Auberton-Hervé, corporate president of Soitec. "This situation means that 200mm fabs will be pressed into service during the transition period to help accommodate volume requirements for manufacturing smaller-geometry devices," he states, adding that as the industry moves to 130nm and below, SOI will succeed bulk CMOS.
 Figure 4. 1992–2002 quarterly IC ASP and unit volumes. (3Q–4Q02 figures are forecasts; source: WSTS/IC Insights Inc.) |
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A major challenge that wafer suppliers face is the increasing complexity of standards associated with the move to 300mm. "Large IC manufacturers issue more than 200 different silicon wafer specs; on 200mm alone, we have more than 500 specifications active in manufacturing," notes Braetsch. "With 300mm getting more into volumes, we feel a clear trend to highly customized individual specs."
Besides complexity, wafer suppliers feel the pinch from added costs of the transition. "MEMC doesn't expect parity with 200mm," says Kauffmann. "Unlike IC manufacturing, wafer manufacturing doesn't scale. For 300mm, you need a larger crystal puller, a slower cutting rate, more material removal — the lapping and polishing — and so forth." 300mm specs are very different from those for 200mm. For example, nanotopography, a new 300mm requirement, needs a different set of equipment to measure the attribute.
Click here to view 300mm fab watch
Equipment
IC manufacturers did not hide their initial disappointment with 300mm tools. "Although a few suppliers have designed higher-performing 300mm tools, many still have the same fundamental manufacturing limitations that we saw on 200mm processes," states Bruce Sohn, manager of Intel's Fab 11X, Rio Rancho, NM. "We must design advanced tools with the expectation that they will operate smoothly at high volumes, high reliability, low defects, and low overall costs. It is far too costly to continuously develop tools to meet basic requirements after the equipment is in production." Even though the tool sets are not totally meeting IC manufacturers' expectations, the industry marches on. Semico Research estimates that 300mm equipment investments in 2002 will be $11.3 billion, with Intel expected to lead the way at $3.0 billion, then TSMC at $1.3 billion [1]. UMC and Infineon are projected to spend $1.0 billion, with everyone else less than that.
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One aspect to the 300mm transition is the growing need for single-wafer processing tools. "There are strong economic drivers for the use of single-wafer processing tools," states Michel Morin, VP of marketing and sales at INCAM Solutions. "The primary driver is cycle-time reduction. . .the use of single-wafer processing is also fueled by ASIC and SOC applications that will stress the regular batch fab operations to deal with quick turnaround multiproduct manufacturing." He goes on to explain that single-wafer handling, by design, delivers random access to all wafers in stockers and buffers. "This makes it possible to use some short-time production slots available to process single-wafer lots. Single-wafer handling systems do not need the complex dispatching strategies and the sophisticated scheduling policies of batch systems."
Another important trend getting a boost in the migration to 300mm is e-diagnostics. Being able to collect data, i.e., e-diagnostics, and how it flows, will be critical to making the 300mm transition according to Dave Faulkner, executive VP of Cimetrix. He also points out, however, that, while the Semi 300mm standards are a driver for successful fab integration, each fab has created its own interpretation of the standards. "Equipment manufacturers need to have a modern software architecture that can easily be adapted to subtle changes for each IDM," states Faulkner. "Resolving differences on the fab floor is not the answer."
Conclusion
It is clear that finding profitability in 300mm manufacturing will not be easy. Start-up and ramping costs, mask costs, and defect/yield challenges remain. And all of these things have to be accomplished in the midst of materials changes and a downturn. The coup de grâce: China may not be the pot of gold the industry is expecting.
With the migration to 300mm, the industry seems to have evolved from a strategy that pits IDMs against foundries to one more akin to collaboration and alliances. Not that all of the cost-sharing and relationship-building has taken place in a spirit of altruism. Rather, the sheer magnitude of the transition along with the aggressive feature shrinks and change in materials, have combined to almost force a new way of doing business. In spite of all the challenges, analysts remain optimistic about the future of 300mm.
References
- 300mm Wafer Production: The Lord of the Wafers, Semico Research Corp., 2002.
- The McClean Report 2002, IC Insights Inc.
Debra Vogler, Senior Technical Editor, Solid State Technology, e-mail [email protected]
Mask cost containment strategies
To save on mask costs, Chartered Semiconductor encourages the use of shelf-proven IP blocks and running one or two products on a shuttle to avoid spending money on a reticle set that has yet to be proven. Because multiproject wafers only address the evaluation or prototype phases, the fabless or fab-lite clients need not make their decision as to whether or not to go with 300mm wafers (instead of 200mm) in advance, asserts John Martin, CTO of the company. "But mask cost is only a part of the cost — it's not the dominant factor over the life of the product. Rather, it's a barrier to entry," explains Martin. "It's not 300mm vs. 200mm. It's the feature size that raises the reticle cost."
While most foundries still make use of the multiproject wafer concept as a way to save customers money on reticles, there are limitations. According to Keith Gronlund, senior marketing manager at ASML MaskTools, "The strategy will work best with the attenuated PSM, chromeless phase lithography, and binary reticle types. It will probably be less feasible for complex two-exposure reticle strategies such as alternating phase shift mask (altPSM) and double dipole lithography."
Yet another cost savings strategy is being emphasized by Numerical Technologies as the industry moves to 300mm. In the pre-300mm processing environment, reticle inspection revolved around an "inspect all, repair all" philosophy, notes J. Tracy Weed, senior director, marketing and business development. "Given the complexities associated with 300mm wafers, especially those at the 0.13µm and below nodes, reticle inspection has evolved toward the 'inspect all, repair what prints' strategy in which all reticle defects are automatically identified and classified, with only the most egregious flagged for repair."
Acknowledging the technology leaps required to improve defect detection for 300mm manufacturing, Steven Carlson, senior VP of technology at Photronics, believes that intelligent mask inspection and automated defect detection in real-time significantly bolster time-to-market and are vital elements of the overall fab cost equation. "Reticle rework poses a negative for mask manufacturers, but it also represents a significant productivity and cost obstacle for the IDMs and foundries," states Carlson. "The challenge to both of these constituents is clear: reduce the mask anomalies, simulate the final silicon, and accurately classify/correct the offending defects."
To that end, companies that make mask repair tools are being called on to perform in an environment that leaves little room for error as the industry moves down the roadmap to smaller and smaller geometries while simultaneously migrating to 300mm. "The only thing that changes from 200mm to 300mm wafers with respect to the photomask is the number of shots printed on the wafer," explains Rey Brannen, product manager at FEI Co. "However, as strong phase shift technologies become more popular, it is necessary to repair unwanted phase shift errors caused by quartz phase bump defects. Complex optical proximity correction features must also be repaired along with smaller defects that previously could be ignored or were not detectable at larger nodes."