VSEA symposium provides perspective on implant roadmap
09/01/2002
VSEA symposium provides perspective on implant roadmap
Three-dimensional SOI, planar/vertical double gate transistors will be ready in the next few years (Fig. 1), said John Borland, director of advanced business development at Varian Semiconductor Equipment Associates (VSEA). Borland chaired the company's technical symposium at Semicon West, where he outlined the evolution from single-gate structures to double-gate SOI CMOS.
"The key to extending planar single-gate CMOS and the realization of double-gate CMOS will be source drain engineering," said Borland. "The lateral graded single source drain structure - either terraced or wedged - is one potential solution."
To get to the 90nm node, Borland asserted that RTA high-temperature activation will work, but at 65nm and below, low temperature activation (SPE) is preferred. The end of classical CMOS scaling should occur by about 2016, at the 22nm node.
Material issues with SOI are not expected to be an issue, said Borland, especially if the expected improvement in device performance is cost-competitive for high-end/high performance CMOS logic. "Everyone is still watching to see when Intel switches to SOI," Borland added, although he thought lower end MPU will still be bulk CMOS. Presenter D.K. Sadana, of the T.J. Watson Research Center at IBM, said he believed that high-volume production of 300mm SOI will occur by 2005.
IBM's Ghavram Shahidi emphasized the advantages of using SOI for RF applications, noting that SOI enables much higher isolation and reduces cross-talk. "It's easier to fabricate vertical SiGe bipolar on SOI than on bulk CMOS," explained Shahidi.
Borland's opening question at the symposium was, "What's missing from the roadmap from an implant perspective?" Professor Hiroshi Iwai, Tokyo Institute of Technology, thought there should be several roadmaps that correspond to different applications (Fig. 2).
"It would be a huge effort, but we need more investigation and discussion of USJ souce/drain issues for the roadmap," said Iwai. "We first need to come to a conclusion for the basic, high-speed logic roadmap...but the sheet resistance could be higher for some of the other applications."
Borland concurs with Iwai, adding that the industry roadmap focuses on pre-competitive issues: "I think they view the multiple roadmaps as very competitive right now and so, until they become standard and used by many, the committee and working groups will not discuss them in detail."
 Figure 1. Single-gate evolution to double-gate SOI CMOS. Source: VSEA |
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 Figure 2. Different roadmaps for different applications. Source: H. Iwai, Tokyo Institute of Technology. |
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KLA-Tencor takes on matching overlay for 300mm
A new software option, Archer Analyzer, for KLA-Tencor's Archer 10 optical metrology tool, allows automated real-time analysis of overlay metrology data for 300mm wafers (and 200mm wafers). The company targeted 300mm lithography due to the high degree of complexity involved in matching overlay. In particular, the effect of overlay errors is directly proportional to wafer diameter, so it is crucial to address 300mm needs. "Rotation and magnification errors, for example, have about a 50% greater impact on 300mm wafers than on 200mm wafers," says Chris Mack, VP of lithography technology.
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Also, as the industry heads for the 130nm node, being able to control CD and overlay will be necessary to control yield. - D.V.
Semicon West lively Lithography
At the recent Semicon West, lithography tools, films, and techniques livened up the show.
Applied Materials described its Advanced Patterning Film (APF), a removable hard-mask/BARC layer that allows less robust 193nm resists to successfully pattern sub-50nm transistor gates.
The APF is a 2 layer stack: amorphous carbon covered by a SiON DARC anti-reflective layer on which conventional resist can be spun and processed. After the resist is developed, a fluorine dry etch transfers the pattern to the SiON layer. The resist is stripped and an oxygen ash process removes the hard carbon layer from the SiON's openings. A polysilicon etch process then transfers the pattern into the gate electrode layer and also consumes the remaining SiON.
A final oxygen ashing removes the last trace of organic material. This process adds four or five vacuum processing steps (two CVDs and two or three etch/ash steps) to a conventional wet-chemistry resist process, but enhances the etch resistance of thin and delicate photoresist films. Farhad Moghadam, a VP and GM at Applied, claimed that APF allows chipmakers to extend the current 248nm gate and contact technology beyind the 130nm node.
Carl Zeiss has long produced a line of aerial image metrology system (AIMS) tools for analyzing the printabilty of reticle defects, but those manual review tools have been famously difficult to use. At Semicon West, the company showed an automated defect review station, the AIMS Fab Plus, which can image and determine the importance of previously located reticle defects at a rate of 1 site/sec. By determining whether an apparent reticle defect (or repaired defect) will in fact print on wafers, automated AIMS tools may improve confidence in the less-that-perfect masks, lowering reticle costs.
Leepl Corp., a joint venture between Tokyo Seimitsu and NTT Advanced Technology, is developing the controversial Low Energy Electron Projection Lithography (LEEPL) technique. It shared a booth with Accretech's fast inspection tool for 1×membrane masks.
The system printed 50nm contact arrays, and LEEPL inventor Takao Utsumi expects to see a throughput of 45 300mm wafers/hr. Fabricating the 1× masks remains a concern, but the Accretech inspection tool - which runs 10× faster than conventional systems because it involves 10 SEMs operating in parallel - should speed things up. FIB technology and gas-assisted electron beam systems can repair the reticles once defects are found. - M.D.L.
Cu CMP system launch and market
NuTool's CEO and founder presented data from Dataquest at the company's Semicon West launch of its Cu CMP system, LuminaCu RL-CMP. Homayoun Talieh showed a target production volume ramp for the industry of $2.81B in FY04/05. The Cu CMP market segment is ex pected to have a CAGR of 25% between 2002 ($1.433B) and 2007 ($4.457B). The new copper CMP system uses a reverse linear belt motion and is designed to polish both Cu and barrier metals at the same polishing station, It also has very low dishing and almost no global oxide loss, added Talieh.
Talieh also reported that the company is undertaking at its facilities - per customer request - an STI demo using the new tool. Other (unspecified) customers for the new product include three in North America, one in Europe, and one each in Taiwan and Japan.
Dean Freeman, principal analyst at Gartner Dataquest, said that offering a Cu CMP solution is a logical step for the company to take - NuTool already offers an ECMD (electrochemical mechanical deposition) solution.
Noting that the product appeared to be the first fixed abrasive tool for Cu, Freeman said that NuTool needs to leverage TEL's sputtering group for barrier seed so it is not dependent on Applied Materials and Novellus for this capability. (NuTool has alliances with TEL and ASMI; see figure.) Noting that shearing issues come into play with porous low-k materials, the question is which CMP technology will work effectively - and that is still to be determined.
"NuTool might be a good step in the direction," stated Freeman. "The proof is when you get multiple orders from multiple clients."
 Combined results of ECMD and RL-CMP with ASMI's Aurora Low-k dielectric. On the left is an FIB e-beam image; on the right, an FIB ion beam image. |
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