IEEE VLSI Symposia: Hot tech in tropical locale
08/01/2002
For 22 years, semiconductor engineers from both sides of the Pacific have met at the IEEE VLSI Technology and Circuits Symposia, mostly in Hawaii. This year's meetings took place in Honolulu, and despite the worst industry downturn ever (travel restrictions, etc.), 551 people attended the technology symposium, down only a bit from last year's record high. More than half were from outside the US, with Japan contributing the largest contingent, both in papers and attendees.
In spite of the glorious tropical surroundings, most attended the all-day sessions on such advanced topics as SOI, CMOS scaling and reliability, high- and low-k dielectrics, and new memory types.
Dimitri Antoniadis of MIT gave the technology keynote speech, "MOSFET Scalability Limits and 'New Frontier' Devices." According to Antoniadis, scaling down devices' silicon MOSFETS to 10nm gate lengths will not produce the expected speed improvements unless new materials and structures are adopted to increase carrier velocities. Without that, too much of the maximum (universal) mobility will be consumed by vertical electric fields due to doping gradients and by scattering.
Mobility can be improved using strained Si gate layers, SiGe material, creating undoped channels using fully depleted SOI structures, and other innovations. The carrier velocity also influences the leakage (off) current of a gate; a 22% velocity increase gives a 100-fold reduction in power-wasting off-current. Beyond 2012, industry projections will require fully ballistic channels as well as greatly reduced contact resistances, possibly achievable using carbon nanotube FETs, according to Antoniadis.
Mobility enhancement turned out to be one central theme of the symposium. Ken Rim of IBM described his team's fast NMOSFET with a strained Si channel and a high-k (HfO2) gate dielectric separated from the channel by a SiON spacer. The leakage was greatly reduced by the gate dielectric and the strained silicon counteracted the speed reduction from Coulomb scattering introduced by the dielectric.
A path towards integrating medium-high-k dielectrics was presented by L. Columbo of Texas Instruments. TI's material, HfSiON, has a dielectric constant of 12-15, but mimics the best features of SiON gate dielectric: It is amorphous, blocks boron diffusion, works even with 950° anneals and realizes 80% of the universal mobility at high field!
Even so, TI senior fellow Bob Doering does not expect it to be used until the 65nm generation.
Memory density was another theme: Two six-transistor SRAM cells with areas just below 1μm2 were presented as well as DRAM innovations. The "scalable" high-density embedded SRAM technology from Matsushita presented by K. Tomita used no angles or bends in the layout, nine layers of Cu (four of them with low-k ILD), and other innovations to get good performance at 0.998μm2 area. Vertical transistors shrank the sizes of DRAM cells made with 100nm and 110nm ground rules. Rajesh Rengarajan of Infineon described how an IBM-Infineon team had integrated logic devices into such a DRAM process. Hyunpil Noh of Hynix presented a 0.08μm2 DRAM cell with a tungsten gate and a Ru-Ta2O5 capacitor, patterned using ArF lithography.
The most innovative process was perhaps the one producing 50nm gate-all-around (GAA) devices and bulk MOSFETs on the same chip. Stephan Monfray of STMicrolectronics and France Telecom described a "silicon-on-nothing" gate fabrication technology in which a sacrificial epitaxial SiGe layer is grown on the silicon substrate, patterned, and then covered by an epi-Si layer that will form the channel of the GAA device. That layer becomes poly-Si where overlays previously formed STI areas. After the gate stripes are patterned, the SiGe is etched out, leaving a Si bridge, and the gate oxide is formed on the bridges and substrate. Poly-Si is then deposited to form the gates for both the GAA and bulk-Si devices on the substrate. Conductive amorphous silicon finds its way under the bridging channels and forms the bottom gate of the GAA devices.
Lithography
Patterning remains an issue in VLSI technology where the viewpoints of the Japanese and American companies seem to differ. Matsushita Electrical Industries, for example, is more concerned with low-power consumer products than PCs.
Takahiro Matsuo of Matsushita described the advantages of electron projection lithography (EPL) for the chips required. At the 65nm node, EPL promises to make the required 85nm contact holes as well as 70nm lines at various densities with adequate exposure latitude and no DOF issue. In contrast, 193nm and 157nm optical lithographies — even with attenuated-PSMs and quadrupole illumination — do not appear to provide acceptable margin. The issue is whether EPL can achieve the projected 30 wph throughput at a 40nm beam blur.
If not, Akio Misaka, also of Matsushita, is ready with two new powerful resolution enhancement technologies — outline PSM (OL-PSM) and centerline PSM (CL-PSM) — each requiring a tuned illumination system for best results. The OL-PSM system uses a semi-transparent substrate with zero phase along with 0° and 180° phase-shifted transparent regions to enhance edge contrast. The centerline system emulates a variable attenuation att-PSM by placing variable-width 180° shifter regions in the centers of dark lines. Simulations indicate that these innovations may allow high-NA ArF systems to pattern 65nm node patterns.
Seiro Miyoshi of ASET described processes to fabricate 65nm node gates using 157nm lithography and a way to overcome the low etch durability of fluoropolymer resists either by using hard masks or silicon-containing bilayer resist. This early report on the performance of the Excitech NA=0.85 microstepper was very encouraging, with 85nm dense line-space patterns easily produced and 55nm lines seen.
At a rump session panel discussion organized by Peter Silverman of Intel and moderated by Paulo Gargini (Intel) and Wakaru Wakamiya (Selete), experts discussed whether 157nm was really necessary (in light of probable delays) and whether the industry should just skip a generation and go directly to EUV. David Kyser of AMD pointed out that skipping a technology generation has proven fatal for technology vendors, most recently for SGVL.
Shinji Okazaki of ASET made the case that the EUV technologies were at least as inexpensive as corresponding 157nm technologies, except for the source, which presently requires megawatts of input power. A 100-fold improvement in source technology would end the debate in EUV's favor, according to Okazaki. He predicted that problems with imaging flare would be irrelevant for contacts or overcome using negative resist for gates and nearly constant duty factors for interconnects.
Others pointed out that ArF technology could be kept viable to 65nm or even 55nm half-pitch, leaving only a small uneconomical window for 157nm lithography at the 45nm leading edge. Masaomi Kameyama of Nikon dismissed that as a concern, believing that long wavelength exposure would always be cheaper for noncritical layers, even if the long wavelength was 157nm!
From the point of view of a tool user, the situation at the 65-45nm nodes is ideal, according to Gargini. With three exposure wavelengths (193nm, 157nm, and 13nm) competing, users will be able to choose the very best technology at the best price. Outside the US, investments in VUV and EUV infrastructure are seen as an appropriate use of government funds and so money to develop those technologies is not an issue, according to Gargini.
Of course many of those same governments have invested heavily in supersonic transport airplanes and highways to nowhere. Cable television subscribers have the choice of many channels, not one of which has the resources to do anything distinguished. The panel concluded that it is unlikely that either 157nm or EUV would be abandoned, but it is at least debatable whether either will be implemented on the currently foreseen schedule or without further drama. Keeping Moore's Law going in the interim will likely require cleverness with older lithographies.
Circuits
At the Circuits Symposium, attended by 358 engineers, mostly from overseas, Takakuni Douseki of NTT foresaw a new environment dominated by ultra-low-power CMOS/SOI designs for ubiquitous short-range wireless networks. If the power consumption is so low that batteries are unnecessary — or never need to be changed — everything can communicate with everything else all the time, changing the way we live. Building such devices would revive the industry, but the chips would be complex, with three transistor threshold voltages, as well as new logic, power supply, and analog circuits. However, the laboratory results are promising, according to Douseki. — M.D.L.