No clear low-k winner at IITC, ISMT Workshop

08/01/2002

A heated debate by attendees of the recent International Interconnect Technology Conference (IITC) and International Sematech's Ultralow-k Workshop did not give supporters of either SOD dielectric films or CVD films a definitive victory.

Other significant areas highlighted at IITC include failure issues surrounding Cu interconnect systems during thermal processing and electrical stress, the increase of copper resistivity with reduced feature size, and copper's impact on intermediate and global wiring.

Honeywell Electronic Materials CTO Michael Thomas believes that a key area covered at IITC is the use of more sophisticated dielectric stack technologies using low-k effective approaches vs. the k value of individual dielectric materials.

"Present approaches using cap and etch stop layers of SiC- and SiN-based materials, having k values between 4.5 and 8, impose a large penalty on the k_eff of dielectric stacks and are far from being low-k materials," Thomas says. "By using chemically dissimilar materials, which all have low-k material properties between 2.0 and 3.0, it is possible to attain very low-k_eff and manufacturability advantages — built-in etch stops and caps that provide added etching and lithography control."

The IITC had a separate section covering optical interconnects. The industry still has much to do if it hopes to meet roadmap requirements for optical interconnects. "While there will probably be some working prototype devices incorporating optical interconnects by 2005, it's doubtful that this technology will be ready for large-scale production at that time," comments Thomas.

While not trying to guess the future, he believes that the first use will be in a hybrid application for very high frequency device applications (microprocessors and ASICS) that require rapid global on-chip routing of signals.

"Part of the problem with bringing on-chip optical interconnects to production is that all of the optical system components need to be mature and compatible, with all integration issues addressed," explains Thomas. "You'll need stable, well-characterized light transmitters and receivers, integrated fiber optic on-chip and electronic circuit designs that take advantage of the speed and power afforded by the system."

On the SOD vs. CVD debate, Mark McClear, GM of semiconductor fab materials at Dow Chemical Co., is convinced that the papers presented at these two conferences clearly demonstrated that spin-on low-k materials are now being used in volume production.

"Moreover, those companies — IBM, Fujitsu, and Sony — that have developed copper and low-k integration processes with high yield for the 130/90nm nodes are at least one generation ahead of the rest of the industry," states McClear. He believes that these companies will have less difficulty delivering the 90- and 65nm technology nodes in 2003 and 2005, respectively.

But a CVD proponent, Trikon Technologies, has a different take on the IITC event. "In general, CVD suppliers were better represented than SOD suppliers with FSG and CVD OSG films at k ≈ 3 being most reported," notes Andy Noakes, CVD products marketing manager at Trikon. "Reality has set in to the manufacturing base as they start to ship the first 130nm product, and they appear to be going for the safety of CVD technology."

Neil Hendricks, chief technologist at ATMI, has a balanced approach to the dilemma, expecting CVD deposition of organosilanes and organosiloxanes to form OSG films with nominal k values of 2.8 to dominate the first post-FSG low-k IMD implementation. While he doesn't expect porous dielectrics to be implemented until the 50nm node, he does believe that if and when porous dielectrics with nominal k values of 2.2 are implemented, the spin-on approach will have a new life.

Meanwhile, International Sematech (ISMT) issued a news release in early June that stated, "Spin-on dielectric materials are considered to be an enabling technology that will take the semiconductor industry to the next level in chip performance." JSR Microelectronics is working with ISMT to provide test wafers using the company's low-k dielectric.

JSR's Chris Klekar, product manager, allows that CVD films are favored right now for device generations that require k ≈ 3.0 to 2.7 because similar processing is used for silicon dioxide and existing toolsets, but, "Porous SOD materials are favored for device generations needing k ≈ 2.5 to 2.0," states Klekar. While integration challenges remain, he notes that test wafers incorporating porous SOD materials are available with single and dual damascene copper structures. Commenting on reports of CVD materials with k values approaching 2.2, he believes that wafer-to-wafer consistency of the CVD films compared with SOD materials at equivalent k values has yet to be proven.

A great deal of attention is focused on porous low-k materials, but one company, Dielectric Systems Inc. (DSI), is gaining notice with its nonporous film (k sub 2.7) — just not at IITC.

"When individual speakers were approached with questions regarding opportunities to work with a nonporous, k = 2.2 dielectric, high-modulus film, it was like asking if they have seen a unicorn," comments Chris Nygren, worldwide director of marketing and sales at DSI. Nygren noted that porous SOD films seemed to dominate the talks, but missing were packaging and CMP mechanical property requirements, barrier solutions to sidewall pore size and density issues, as well as other hurdles in the integration roadmap.

One IITC paper that captured attention was a joint presentation by IMEC/XPEQT and the Paul-Drude-Institut für Festkörperelektronik. Most chip process developers use Young's modulus as a determining factor in whether or not a porous dielectric is suitable for integration into a damascene/CMP process flow, so understanding the relationship and having accurate measurements is important.

"These researchers showed that the nano-indentation technique consistently overestimates Young's modulus for porous thin films by a factor of three or more," explains ATMI's Hendricks. "A variety of non-destructive acoustical and optical techniques were shown to provide accurate, reliable, and much lower Young's modulus values when compared to nano-indentation."

Loren Chow, a low-k technologist at Intel, brought the ISMT ULK workshop conference down to earth with his comment that the industry will not change ILD materials unless there is a clear need. He described a series of tests used to evaluate, screen, and examine integration feasibility of new ULK materials. Intel is pushing for materials and equipment suppliers to perform phase one of the set (k value, film stress, outgassing, adhesion, etc.) before contacting customers about using the new materials.

Intel's Makarem Hussein presented a paper that compared sacrificial light absorbing material (SLAM) to BARC-assisted dual-damascene patterning. The BARC-assisted patterning showed shell defects while SLAM achieved defect-free performance. The company expects to extend the technology below 130nm, although Hussein notes that sensitivity to dry and wet etch chemistries will have to be addressed.

Both conferences presented clear indications that IC manufacturers will have to choose less than perfect solutions if they are to continue down the roadmap at speed. IMEC's Marc Heyns believes that engineering-type solutions will have to fill the gaps in integration issues that are not yet scientifically understood.

"Trade-offs might have to be made in terms of various performance parameters such as speed and power consumption," says Heyns.

John Iacoponi, low-k dielectrics program manager at ISMT, explains that while the availability of materials with k ≈ 2.0-2.2 is increasing, complete integration of them into a Cu/low-k interconnect structure is especially difficult for six to 10 levels of Cu interconnect.

"Slips in low-k implementation as predicted in previous revisions of the ITRS roadmap can be attributed to the complexity of the challenge of integrating Cu with low-k materials," he notes.

Perhaps summarizing the feeling of many, IMEC's Karen Maex comments, "The question is not so much whether the materials are available — there are many materials available. The real problem is that the integration of them has required more time than was foreseen." She further notes that the outcome of the sealing efficiency, barrier, and dielectric integrity will be very important in the decision-making process and in assessing how low k values can go. — D.V.