Custom production problems challenged by direct-write e-beam system
07/01/2002
By Katsuya Okumura, University of Tokyo
Kazuyoshi Sugihara, Ichiro Mori, Process and
Manufacturing Engineering Center, Toshiba Semiconductor
We have developed the basic technology for a high-throughput, direct-write e-beam lithography system. The direct-write approach avoids the problem of the US$1 million mask set, and we think we can match the production speed of a KrF excimer laser scanner (Fig. 1).
 Figure 1. New e-beam direct-write technology could reduce mask production time and process time. (Source: University of Tokyo and Toshiba Semiconductor) |
Though direct-write seems like an ideal solution for avoiding high mask costs and getting custom chips to market faster, in practice, throughput has been too low to be practical. Though variable-shape beam systems are an improvement, it still takes 2.9 hr to expose one 200mm wafer, when an optical scanner can do the job in minutes.
We've mapped out an approach to speed up the e-beam process at every step, using a low-energy e-beam source, small multipole lenses, in situ cleaning, character projection, and simultaneous measurement of alignment. Simulation suggests the low-energy source, asymmetrical electrostatic lenses, and in situ cleaning can increase throughput to 39 min/wafer. Reducing the shot count by character projection can improve it further, to 6 min/wafer. Cutting inspection and alignment time can make up the rest of the difference.
The most time-consuming part of the e-beam writing process — and therefore the most important to reduce — is resist exposure, which takes up 48% of the total time. Using a lower-energy e-beam directly improves resist sensitivity, as most resist reaction is with the slower secondary electrons. The low-energy beam has a larger impact surface that produces more secondary electrons. If the e-beam energy is reduced from the usual 50keV down to 5keV, the sensitivity of the resist improves tenfold.
Though the low-energy beam cannot penetrate all the way to the bottom of a 1μm layer of resist, resists are getting thinner. Current 0.18μm processes use 0.4-0.3μm layers of resist, and the next generation is likely to get down to 0.2μm. These thin resists can easily be penetrated by a 5keV e-beam.
A more serious problem with low-energy e-beam is the blurring caused by coulomb interactions as intensity increases. We solve this with a new electrostatic lens using asymmetric optics. This small multipole lens has little aberration even at high intensities. Since a symmetrical lens produces the greatest blur at the cross point of the optical axis, we designed an asymmetrical lens to create an e-beam column that is not the same in the x and y directions. Since the beams are never concentrated at any one point, beam blur is greatly reduced (Fig. 2).
 Figure 2. An asymmetric multipole electrostatic lens system improves resolution. (Source: University of Tokyo and Toshiba Semiconductor) |
To further improve resolution, we use a cold cathode electron gun. This requires a super-high vacuum, for which we use a small coaxial-type ion pump. The electron gun within the cathode of the ion pump can produce a 10-10 Pa-level vacuum. Instead of the usual cone-shaped cathode, we use a linear one, which further reduces coulomb interactions and blur.
By using only electrostatic lenses, we can make the lenses very small, with a volume of only 200cc. The short beam length further limits coulomb interactions and reduces blur. Current resolution is sufficient for the 70nm node and should be extendable to 50nm.
The low-energy system also requires less voltage to deflect the beam — the small lenses reduce it even further. Lower deflection voltage means faster deflection time. Reducing the deflection voltage from the 200V needed by high-energy e-beam down to 20V reduces beam deflection time from 100μsec down to only 0.4μsec.
We prevent problems with electrostatic charge by in situ cleaning. Since the main cause of electrostatic charge is carbon buildup in the lens, we developed a method to remove this carbon by an in situ downflow cleaning process.
We also developed exhaust technology to reduce the need for such cleaning, and are working on making e-beam lenses of a new material we have developed that resists electrostatic charge. Without the beam drift from electrostatic charge, we do not need chip-by-chip alignment, greatly reducing alignment time. Using these technologies, we have written 140nm-pitch line patterns.
Though these improvements in the e-beam itself can increase throughput to 39 min/wafer, reducing the number of shots required can further speed up the process.
We use the character projection method, which breaks up patterns into small, often-repeated blocks, or characters, that can each be written in one shot by shaping the beam appropriately. One such pattern that takes 18 shots to be written with a variable-shape beam tool, for example, can be written with only one shot through a character aperture. The process should potentially reduce total shot count by about a factor of ten.
Remaking a whole library of standard logic cells into characters — dividing each cell into four characters — would be unwieldy, however. So instead, we have reduced our basic library of logic cells to about 100, and primarily designed chips using these cell characters, with others added as needed for extra functions. Though these limited building blocks do mean the design sometimes uses more space or achieves less speed, fewer cells can also mean simpler and faster design changes, as well as easier integration.
The method also reduces shot count for other repeated blocks like memory, interconnects, and vias by about a factor of ten. Character projection works especially well with low-energy e-beam, because lower-energy beams do not produce the proximity effects that interfere with neighboring patterns. Thus they do not require multiple shots or corrections.
A final improvement in throughput comes from reducing the time needed to inspect, measure, and align the system. The low-energy e-beam can also be used for scanning electron microscopy (SEM) inspection.
SEM measures the capacitance contrast — the difference in electrical potential on the wafer surface — to check the pattern alignment. It uses the latent image contrast — the change in the resist on exposure — to measure dose and dimensions.
These simultaneous in situ measurements take only tens of seconds. That cuts the total raw process time for a 25-wafer lot down to 186 min plus this brief in situ inspection time, still more time than the 106 min required by the KrF scanner. But the e-beam system can process a four-wafer lot in only a little more than 60 min, while the scanner takes 85 min.
This article was translated and condensed by Paula N. Doe from the March 2002 edition of Nikkei Microdevices, our partner in Japan.