New research yields epitaxially grown GaAs on Si
07/01/2002
By Kurt Eisenbeiser, Ravi Droopad, Jeff Finder, Motorola Labs, Tempe, Arizona
Overview
A new process epitaxially grows a compound semiconductor material, such as gallium arsenide, on a standard silicon substrate. This process can be used to form high-performance compound semiconductor devices on selective regions of silicon, thus enabling the monolithic integration of these two technologies. Compound semiconductors have some unique advantages over silicon, especially in optical and RF applications.
Efficient light emission is very difficult to achieve in Si due to its indirect bandgap. The band structure of Si causes electron mobility to be significantly lower than in some other semiconductors, and the bandgap of Si may limit it in high-temperature or high-voltage applications.
In contrast, some compound semiconductors GaAs, InGaAs or GaN provide very efficient light emission, very high electron mobilities, and good high-temperature high-voltage operation. However, these materials suffer many deficiencies compared to Si. Substrates are generally smaller, more brittle, more thermally resistive, or more expensive than Si. The lack of a good native oxide on compound semiconductors severely limits the performance of devices for digital applications.
The ideal situation, then, for increasing the functionality of a Si substrate is to monolithically integrate compound semiconductor devices with Si devices on a single substrate. The potential applications of such a system are numerous. For example, as transistor performance improves, interconnects limit IC performance, but optical interconnects can be a very fast alternative, which has been shown using flip chip or hybrid technology [1]. Optical interconnects could be commercially viable if the transmitter and receiver could be monolithically integrated on Si. Cost, size and parasitics could be reduced.
As another example, compound semiconductor devices can operate at speeds significantly faster than Si-based devices. While there are many tradeoffs due to the drawbacks of the compound semiconductor devices, selective use of these very fast elements in a Si IC can significantly improve overall performance.
Material integration problems
The idea of monolithic integration of Si with compound semiconductors has been around for decades. Significant problems, however, have limited commercial realization. The spacing between atoms in a silicon lattice is significantly smaller than atomic spacing in common compound semiconductors. This difference means that when a relaxed layer of GaAs is grown on a Si substrate, the columns of atoms do not line up and dislocations are formed in the GaAs to accommodate the mismatch (Fig. 1). These dislocations cause degradation in the electronic and photonic performance of the compound semiconductor material.
Figure 1. An ideal Si-GaAs interface; the difference in lattice constant between materials results in misfit dislocations. |
Further compounding mismatch is the very different coefficients of thermal expansion between these materials. When the composite material stack is heated up or cooled down during material growth or subsequent processing, GaAs and Si will expand and contract at different rates, generating more defects and, in extreme cases, delaminating. Past work in this area has generally used thick GaAs or SiGe layers to "grow out" the dislocations [2-5].
With thick layers, many of the dislocations will eventually cancel out, resulting in high-quality layers. Although this technique has been used to produce excellent electronic and photonic devices, the cost ($100s to $1000s/wafer depending on epi thickness and deposition technique) and integration issues associated with thick layers have limited commercial applications. In addition, photonic devices have become less reliable due to the movement of dislocations into active areas during operation.
Oxide buffer layers
We have developed a process that addresses the problems outlined above in a unique way. Our process uses a buffer layer system to alleviate the effects of lattice and thermal mismatch. While buffer layers have been used in the past [6-7], our buffer layer uses a crystalline oxide (SrTiO3 or STO) and an amorphous oxide(SiO2). The crystalline oxide serves as a good crystalline template for growing GaAs, and the amorphous oxide acts as a buffer layer to isolate GaAs from the underlying Si. Using this technology, thin <100Å buffer layers can be used to transition from Si to GaAs.
SrTiO3 has a simple cubic crystal structure with a lattice constant of 3.91Å. The lattice constants of Si and GaAs are 5.43Å and 5.65Å, respectively. While STO may seem to be a poor lattice match for Si or GaAs, this is not the case for properly oriented STO. When the STO unit cell is rotated 45° around the Si surface normal [001] axis, the atomic spacing is 1.8% larger than Si and 2.1% smaller than GaAs. We optimize the growth conditions in our process so the STO is rotated on the Si surface (45° on the [001] surface) so a <100> direction in STO is parallel to a <110> direction in Si. Similarly, when the GaAs is grown on the STO, we rotate back 45° so that the <100> in the GaAs is parallel to the <100> direction in the Si substrate.
The role of the SiO2 layer is equally important in that it improves system compliancy. Work on SiGe growth on silicon-on-insulator (SOI) substrates has shown a significant reduction in defect density in SiGe layers vs. SOI substrates [8]. In this work, it was shown experimentally and theoretically that the lower dislocation energy in the amorphous oxide layer serves as an attractive force to pull dislocations from the interface into the oxide layer and improve the quality of the overgrown SiGe layers.
The SiO2 buffer layer in our structure plays a similar role in the GaAs-on-Si system to improve the quality of the overgrown GaAs. One difference between the SOI system and the STO-SiO2 system is that the STO thickness in our process can be much thinner than the Si layer in conventional SOI. This means that the SiO2 layer can be much closer to the STO-GaAs interface and can serve as a more effective defect sink.
MBE growth process
To grow the various layers, we use a dual-chamber production-type multiwafer molecular beam epitaxy (MBE) system (Fig. 2).
One chamber of the system is dedicated to oxide growth on silicon and is equipped with a 2200 liter/second turbomolecular pump that provides <5x10-10mbar base pressure, obtained using titanium sublimation pumping and liquid nitrogen cryopanelling. For deposition, Sr and Ti metals are evaporated from effusion cells and oxygen is introduced into the chamber through a RF plasma source. The system uses in situ reflection high-energy electron energy diffraction (RHEED) to calibrate fluxes and to monitor the growing surfaces in real-time during the entire process.
The second chamber is a conventional III-V deposition system equipped with a diffusion pump that achieves a <5x10-11mbar base pressure. Elemental sources including Ga, In, Al, As, and Si and Be dopants are available. Growth rates and temperatures are carried out using the RHEED oscillation technique and pyrometery, respectively.
Growing GaAs on Si starts with a clean Si wafer. We heated the wafer to <800°C in the oxide chamber of the MBE system. The wafer is then exposed to a few monolayers of Sr metal flux, a de-oxidation process that results in an ordered surface with no evidence of silicon oxides or carbon. SrTiO3 films are then deposited on the ordered surface at 300-700°C in an O2 partial pressure up to 10-5mbar.
During the growth of SrTiO3, growth conditions, such as substrate temperature and oxygen partial pressure, can be modified to control the growth of an amorphous SiO2 layer at the interface between SrTiO3 and Si. The amorphous layer forms from the diffusion of oxygen through the SrTiO3 layer to the interface where it reacts with the Si substrate. The resulting SrTiO3 is single crystal with low surface roughness of 2Å rms.
The SrTiO3-SiO2-Si sample is then transferred to the III-V MBE chamber where GaAs is grown on the SrTiO3 using Ga metal from an effusion cell and As from a valved cracker. An undoped buffer layer of GaAs is grown on top of the initial GaAs seed layer to electrically isolate active GaAs devices from the Si substrate. GaAs device layers can then be grown on top of this buffer layer using the same techniques and epitaxial structures used in standard III-V devices.
Material, device results
Using double crystal x-ray diffractometry, our process produces a GaAs layer that is single crystal and oriented in the same direction as the underlying Si. A transmission electron micrograph of the structure (Fig. 3) shows the crystalline substrate, the amorphous SiO2 layer, the crystalline SrTiO3 layer, and the crystalline GaAs layer. The surface morphology is excellent with a mirror-like surface when examined by Nomarsky microscopy, an average surface roughness of 9Å for a 10x10μm area, and low defect density [9].
Figure 3. High-resolution cross section transmission electron micrograph of GaAs-SrTiO3-SiO2-Si structure. |
We fabricated a GaAs MESFET as the first demonstration of the device potential for this technology. This device consists of a 1500Å channel doped at 8x1017cm-3 and a 500Å contact layer doped at 5x1018cm-3 grown on top of the GaAs buffer layer. As a comparison, the MESFET structure was also grown simultaneously on standard GaAs wafers. Devices were then fabricated on these samples using standard III-V MESFET processing techniques. Device isolation was achieved by wet etching a mesa.
Ni-Ge-Au ohmic contacts were deposited, patterned by liftoff and rapid thermal annealed to form ohmic contacts to the contact layer. We used a wet gate recess etchant to etch the contact layer from the gate region. The Ti-Pt-Au gate was then deposited by e-beam evaporation and lifted off using optically defined photoresist patterns. The process used on the GaAs-STO-Si sample was identical to the process that fabricated the GaAs-GaAs sample.
Figure 4. Drain current and voltage characteristics for a 0.7x100μm MESFET fabricated on GaAs-STO-Si and GaAs. Gate voltage varies from 0.5V to -1.5V in 0.5V steps. |
We used FETs with 20μm long gate lengths to characterize electron mobility. The GaAs-GaAs control sample had a peak mobility of 2682cm2/Vs while the GaAs-STO-Si sample had an electron mobility of 2524cm2/Vs 94% of the control sample. The output characteristics for 0.7μm gate length MESFETs are shown in Fig. 4. With this work, we concluded that our GaAs-STO-Si devices performed similarly to the GaAs-GaAs devices in all respects.
Monolithic integration
The real potential of this technology most likely lies not with simply making III-V devices on Si substrates, but in the monolithic integration of the III-V devices with Si devices (Fig. 5). To make this integration possible and to minimize risks associated with a new technology, it is imperative to consider not only processing issues associated with integration of III-V and Si based devices, but also logistical issues surrounding location and tooling for this monolithic approach.
Figure 5. Structure for monolithic integration of III-V devices with Si CMOS. |
In the confines of process integration, identifying the ideal insertion point and maintaining substrate planarity are two key issues. Advanced CMOS process designs and device architectures are currently focused around 0.18μm geometries and rapidly approaching 0.13μm and smaller. Given the level of investment in silicon fabs and 300mm equipment development, and the economies of scale experienced with increased wafer size, the CMOS process is relatively fixed so that successful III-V integration will come by molding the III-V process into the CMOS flow.
The issue of the best point in the CMOS flow to insert the STO III-V growth and device fabrication is affected strongly by thermal budgets of the respective processes. The STO III-V process outlined above reaches temperatures up to 800°C during the de-oxidation process. Typical temperatures used during the GaAs growth are up to 600°C. This suggests that if CMOS devices are formed prior to the GaAs material growth, they should only be processed up to about the contact salicide and dielectric passivation with all of the backend interconnection taking place after the GaAs material growth. If this integration path is chosen, care must be taken to adjust implant profiles to account for diffusion during GaAs growth and to address the potential for ohmic contact degradation.
Considering that today dual damascene Cu interconnects dominate the backend processing of high-performance ICs, planarization of the substrate is critical. To electrically isolate a GaAs-based device, a thick undoped buffer layer is required prior to deposition of active layers. This buffer can range from 1-2μm, which substantially changes wafer topography.
Achieving planarity of the GaAs surface with the top surface of the CMOS devices requires that the GaAs-STO-Si interface be recessed below the active regions of the Si. The concept of a recessed GaAs active region has been successfully shown [10, 11]. With this in mind, proper device design, layout, and process control are all variables that must be considered to achieve a planar dielectric surface prior to the interconnect layers.
Besides the basic process issues that need to be addressed when attempting to integrate III-V materials on Si, there are also several manufacturing issues that must be addressed. Most high-volume GaAs fabs use 100mm or 150mm wafers while most state-of-the-art CMOS fabs use 200mm or 300mm wafers.
Monolithic integration then will require either that 200mm or 300mm toolsets be modified for III-V processing or that III-V toolsets be scaled up to larger wafers.
Another possible issue is contamination. III-V materials may be contaminants in Si technology and similarly Si-related materials may be contaminants in III-V technology. The processing of III-V Si substrates then will require careful consideration of these contamination issues in determining the best processing facility for these systems and also in determining the best process sequence. These questions and others will need to be addressed as the technology proceeds for it to become viable and profitable.
Conclusion
Many challenges remain to commercialize GaAs-on-Si technology. Issues with materials development, processing, and manufacturing must all be addressed before this technology can be used in commercial products. The potential payoff makes such an effort worthwhile, however.
The monolithic integration of III-V devices with Si can enable integration on a size and cost scale far exceeding anything possible with the hybrid technology demonstrated to date. With monolithic integration, high-speed III-V digital devices can be seamlessly embedded in Si ICs to give designers powerful new tools to improve circuit performance; RF designers can mix and match III-V RF components with Si and SiGe RF components to achieve optimized RF circuits; and the marriage of III-V photonic devices with Si technology can push Si technology in whole new directions.
The monolithic integration of photonic devices with the unparalleled performance and manufacturability of Si devices can enable not only new interconnection schemes, but also the possibility of integrating optical processing components with the electronic processing components, the possibility of new sensing and output technologies for Si devices, and the possibility of using electronic-photonic interactions on a Si chip to provide new functions not possible today.
References
1. D.A.B. Miller, Proceeding of IEEE Device Research Conf. 2001, pp. 35-38.
2. S.F. Fang, et al., Journal of Applied Physics, 68(7), pp. R31-58, Oct. 1990.
3. J.A. Carlin, et al., Applied Physics Letters, 76(14), pp. 1884-1886, April 2000.
4. T. Aigo, et al., Japanese Journal of Applied Physics, 37, pp. 3205-3209, 1998.
5. T. Sudersena Rao, et al., Applied Physics Letters, 62(2), pp. 154-156, Jan. 1993.
6. R. D. Bringans, et al., Applied Physics Letters, 61(2), pp. 195-197, July 1992.
7. M.K. Lee, et al., Applied Physics Letters, 59(2), pp. 207-209, July 1991.
8. C.W. Pei, et al., Journal of Applied Physics, Vol. 90, no. 12, pp. 5959-5962, December 2001.
9. K. Eisenbeiser, et al., Proceedings of 2001 GaAs IC Symposium, late news addendum, Oct 2001.
10. H. Shichijo, et al., IEEE Transactions on Electron Devices, Vol. 37, Issue 3, Part 1, pp. 548-555, March 1990.
11. H. Shichijo, et al., IEEE Electron Device Letters, Vol. 9, Issue 9, pp. 444-446, Sept. 1998.
Kurt Eisenbeiser received his PhD from the University of Michigan. He is manager of advanced device research at Motorola Labs, 7700 S. River Pkwy., Tempe, AZ 85284; ph 480/755-5240, fax 480/755-5165, e-mail [email protected].
Ravi Droopad received his PhD from Imperial College, London. He is a member of the technical staff at Motorola Labs.
Jeff Finder received his MS and MBA from Arizona State University. He is a senior engineer at Motorola Labs.