Future IC fabrication rests on solutions to circuit and device scaling issues
07/01/2002
Overview
The main scaling goal for high-performance logic is to maximize speed; for low-power logic, it is to maintain low leakage currents. A key issue with scaling is excessive gate leakage current. The introduction of high-k gate dielectric is expected to be driven by meeting the gate leakage current requirements of low-power logic in 2005, while implementation of high-k gate dielectric for high-performance logic is expected to follow shortly. Especially for 2007 and beyond, innovative solutions such as enhanced mobility channels and non-classical CMOS structures may be used, as well as elevated source-drain and associated advanced source-drain fabrication techniques.
By Peter M. Zeitzoff, Robert W. Murto, Howard R. Huff
International Sematech, Austin, Texas
The 2001 International Technology Roadmap for Semiconductors (ITRS [1]) outlines a major acceleration in the scaling of physical (i.e., final, as-etched) gate length (Lg) for high-performance MOSFET transistors (Fig. 1). For example, the projected physical gate length in 2005 is 32nm in the 2001 ITRS compared to 65nm in the 1999 ITRS. This accelerated scaling is driven by the need to maximize chip speed and reflects actual industry trends since1999, which show no signs of abating.
 Figure 1. 2001 vs. 1999 ITRS projections of physical gate length (Lg) for high-performance logic. |
Physical gate length is the smallest transistor dimension, and it engenders an important process control requirement in both the 1999 and 2001 ITRS. The 3-sigma statistical process variation of the physical gate length is not allowed to exceed 10% of the nominal physical gate length. So, the accelerated gate length scaling in the 2001 ITRS poses significantly enhanced challenges to resolution and process control capabilities of both lithography and etch processes.
Driving forces
ITRS device and front-end process scaling is driven by overall chip requirements for improved speed, power dissipation, functional density, etc [2]. Logic ICs fall into two main categories — high performance and low power. Each is used for different applications with different overall chip requirements and, therefore, different scaling goals.
High-performance logic is used typically for high-end desktop and server applications where the main goal is to maximize performance (i.e., chip speed). As a result, transistor scaling and design are aimed predominantly at maximizing MOSFET speed. High leakage current is a necessary trade-off.
Low-power logic is used typically in mobile systems where the main goal is to minimize chip power dissipation, particularly from static, to preserve battery life. As a result, scaling and transistor design are aimed mainly at minimizing MOSFET leakage current; reduced speed is a necessary trade-off.
An important parameter is transistor intrinsic delay (τ), a measure of minimum switching delay in simple logic circuits using the transistor. A formula for τ can be derived in terms of transistor characteristics such as saturation drive current (Isat), gate capacitance, etc. The reciprocal of τ is then a measure of maximum switching frequency for a simple logic circuit using the transistor. 1/τ is called the intrinsic transistor switching frequency and is used as the MOSFET performance figure of merit.
For high-performance logic, the ITRS scaling goal is to ensure that 1/τ increases at an average rate of ~17%/yr, the historical rate. Since 1/τ is proportional to Isat this current must be maximized during scaling. Isat is strongly dependent on gate overdrive (Vdd - Vt), where Vdd is power supply voltage and Vt is threshold voltage. Furthermore, Vdd is scaled down rapidly over successive years, so Vt must also scale down rapidly to maintain satisfactory values of Isat. However, the source-drain subthreshold leakage current (Isd,leak) is strongly dependent on Vt, so as Vt scales down, Isd,leak increases (Fig. 2). Simplified models were used to make these projections and trade-offs [2]. For high-performance chips, the average 17%/yr increase in 1/τ is achieved, but at the cost of a large and rapidly increasing transistor leakage current. For example, the 2001 ITRS projected Isd,leak in 2007 is 1μA/μm, a very high value, and much higher than the corresponding value of 0.04μA/μm from the 1999 ITRS.
Several techniques will presumably be used to keep overall chip static power dissipation within tolerable limits despite such large MOSFET leakage currents. One approach expected to become standard is to fabricate most transistors on a chip with higher Vt and lower leakage current than the high-performance transistors described above. The high-performance transistors are used only in critical paths or in circuits that are constantly switching, while other transistors are used everywhere else. Also, architectural and circuit design-type power conditioning techniques, including turning off inactive circuit blocks, will probably be extensively used to reduce chip static power dissipation. In any case, keeping the chip static power dissipation within tolerable limits for high-performance chips is expected to be an increasingly difficult challenge.
For low-power logic, the ITRS scaling goal is to maintain a specified MOSFET source-drain subthreshold leakage current (Isd,leak), which is chosen to give reasonable battery life for mobile applications. There are two types of low-power logic, low standby power (LSTP) and low operating power (LOP). LOP chips are typically used for higher performance mobile applications such as notebook computers, where battery capacity is relatively large, while LSTP chips are typically used for lower-performance consumer-type mobile applications such as cellular telephones, where battery capacity is relatively limited.
Isd,leak projections for LSTP logic are stringent, at 1pA/μm for 2001-2007, rising slowly to 10pA/μm by 2016. Isd,leak, projections for LOP logic are less stringent, starting at 100pA/μm in 2001 and rising faster than for LSTP in subsequent years.
To maintain the low values of Isd,leak required for low-power logic, Vt must be considerably higher than for high-performance logic transistors. As a result, compared to high-performance logic MOSFETs, the gate overdrive (Vdd - Vt) is reduced for low-power logic MOSFETs and hence Isat and 1/τ are also reduced (Fig. 2). For LSTP transistors, Isd,leak meets ITRS projections and consequently, 1/τ is <40% of 1/τ for the high-performance transistors. (For both 1/τ and Isd,leak, LOP logic transistor curves are between the LSTP and the high-performance transistor curves, but are closer to LSTP.)
It is important to note, however, that Isd,leak is only one component of the overall transistor leakage current; the others are gate leakage current and source-drain junction leakage current. The 2001 ITRS specifies that each of the latter leakage-current components should be smaller than the corresponding projected value of Isd,leak.
Addressing gate leakage current
Leakage current through the gate dielectric is a major scaling issue. Current IC technologies typically use a silicon dioxide film lightly doped with nitrogen (i.e., an oxynitride, where nitrogen is incorporated mainly to minimize boron penetrations and associated Vt instability) for the gate dielectric [3]. The direct tunneling current (i.e., gate leakage current) through the oxynitride gate dielectric increases exponentially as the physical thickness of the oxynitride film is scaled down with succeeding years, and, eventually, gate leakage current may exceed Isd,leak.
To reduce the gate leakage below Isd,leak, various high-k dielectric materials (i.e., those with a relative dielectric constant k considerably larger than that of thermal silicon dioxide) are being actively investIgated as a replacement for oxynitride. Equivalent oxide thickness (EOT) is an important quantity characterizing electrical thickness (excluding quantum mechanical and poly depletion effects) of a high-k dielectric film in terms of an equivalent thickness of thermal silicon dioxide. This quantity is given by
EOT = td x (3.9/k)
where td = the physical thickness of the gate dielectric film and 3.9 is the relative dielectric constant of thermal silicon dioxide (lightly nitrogen-doped oxynitride also has k close to 3.9).
To first order, a transistor with a high-k gate dielectric with a physical thickness td has the same gate capacitance and hence electrical performance in terms of Isat and 1/τ as an otherwise identical transistor with a thermal silicon dioxide gate dielectric of thickness EOT. The gate leakage current, however, is strongly dependent on td, which is larger than EOT for k>3.9. Hence, gate leakage current through the high-k gate dielectric should be significantly reduced from that through a silicon-dioxide gate dielectric, as long as the barrier height between the conduction bands of silicon and high-k material is adequate [4-5].
For LSTP logic, looking at 2001 ITRS projections for EOT and maximum Igate and at detailed numerical simulations of Igate for heavily doped oxynitride (Fig. 3), we see that the simulated value exceeds the maximum Igate target around 2005 (as indicated by the vertical line in Fig. 3). One solution being pursued to meet the LSTP logic gate leakage current targets for 2005 (EOT of 1.8nm and maximum Igate of 1pA/μm) and beyond is to deploy high-k materials (with k ~9-30) for the gate dielectric.
The situation for high-performance logic is different because its requirement that 1/τ increases by ~17%/yr results in much higher projected Isd,leak, values and therefore higher values of maximum Igate than for LSTP logic. Specifically Isd,leak, is four to six orders of magnitude larger for high-performance logic than for LSTP logic (see Fig. 2). Hence, for high-performance logic, detailed numerical simulations indicate that gate leakage current through oxynitride gate dielectric will be large, but within the ITRS projections for maximum Igate through 2016. However, with sub-1.0 nm EOT projected by 2006 and with high levels of gate leakage current anticipated, especially for 2006 and beyond, oxynitride gate dielectric will presumably have major challenges with reliability as well as with process control of the film thickness.
Consequently, while high-k gate dielectrics will probably be initially used for low-power logic in ~2005, it is anticipated that high-k gate dielectric will be deployed for high-performance logic shortly thereafter.
 Figure 4. Simplified cross-section of a high-k gate dielectric stack. |
Areas of concern
There are areas of concern associated with integration of high-k gate dielectric materials into a conventional planar, polysilicon gate process (Fig. 4). The gate dielectric stack encompasses the bulk high-k film as well as the upper and lower interfacial layers, whether these interfacial layers are discrete film types (i.e., silicon dioxide or oxynitride) or graded film layers (i.e., varying composition alloyed mixtures of silicon dioxide or oxynitride with the bulk high-k material). Global issues for this stack include the film deposition uniformity of each layer, including thickness and stoichiometry, the EOT of the entire stack, physical and electrical thermal stability, and the reliability.
Of particular concern at the lower interface are substrate-dielectric reactions, surface roughening, and mobility degradation. With the bulk high-k film, issues that must be resolved include intrinsic defects leading to higher leakage current, and fixed charges and charge trapping in the bulk and at interfaces. Both fixed charges and charge trapping can cause Vt shifts, while charge trapping can cause instability and hysteresis as well.
Other issues requiring resolution are phase separation and crystallization, which may lead to paths for increased gate leakage current, dependent on the varying thermal budgets. Also of concern are stoichiometric changes to the film itself, resulting in a change in k value, which leads to a change (usually an increase) in EOT. At the upper interface, boron penetration must be minimized, as well as dielectric-electrode material reactions. Elimination of the polysilicon depletion effect in the doped polysilicon gate electrode is a concern that is expected to be addressed with the introduction of metal gate electrodes by 2007 (a 2001 ITRS prediction).
The leading candidate for high-k gate dielectric is currently hafnia (HfO2), either in the binary oxide form or as an alloy with either silicon dioxide or aluminum oxide. Zirconium-based films have been found to be thermally unstable because of material interactions between the high-k material and the polysilicon gate electrode, and do not appear to be viable candidates at this time [6-8]. As a result, the current emphasis is on finding solutions to the above issues using Hf-based high-k films [4].
Potential innovative solutions
So far, we have assumed that difficult challenges with highly scaled devices, such as control of short-channel effects and simultaneously achieving adequate saturation current drive and tolerably low leakage currents, can be overcome. However, innovative solutions to these challenges may be needed. One approach under development uses strained silicon on relaxed silicon-germanium layers to increase effective mobility and hence to increase the saturation drive current of MOSFETs. Dynamically or electrically alterable threshold voltage techniques, in which the threshold voltage is varied to be low when the transistor is on and high when it is off, are also being explored. This could be very helpful in improving the trade-off between performance and source-drain subthreshold leakage current.
In addition, owing to difficulties in scaling the source-drain, techniques such as elevated source-drain and associated advanced source-drain fabrication may be used, particularly beyond 2007 [9-10].
 Figure 5. Simplified cross-sections of MOSFETs, including nonclassical structures. |
Finally, beyond 2007, it is anticipated that classical planar bulk CMOS devices will have increasing difficulty in meeting MOSFET device requirements, especially because of difficulties in fabricating ultra-small devices and in controlling short-channel effects in them, and because of the increasing impact of quantum effects and statistical fluctuations in both the number and location of the dopant atoms. Non-classical CMOS structures (Fig. 5), such as fully-depleted SOI with a very thin silicon layer, double-gate SOI, and vertical MOSFETs, are being developed, and may be effective in dealing with these issues [11-13].
References
1. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS) 2001 Edition, Austin, TX: International Sematech, 2001 (http://public.itrs.net).
2. P.M. Zeitzoff, et al., IEEE Circuits and Devices, Vol. 18, pp. 18-27, March 2002.
3. A. Karamcheti, et al., Semicon. FABTECH, 12th ed., pp. 207-214, June 2000.
4. H.R. Huff, et al., Proceedings of International Workshop on Gate Insulators (IWGI), Tokyo, Japan, November 2001.
5. G.D. Wilk, et al., Journal of Applied Physics, 89, pp. 5243-5275, May 2001.
6. A. Agarwal, et al., Proceedings of Materials Research Society Symposium on Gate Stack and Silicide Issues in Silicon Processing II, S. A. Campbell et al. ed., MRS Vol. 670, pp. K2.1.1-K2.1.11, April 2001.
7. K. Onishi, et al., IEDM Technical Digest, pp. 659-662 Dec. 2001.
8. C. H. Lee et al., IEDM Technical Digest, pp. 27-30, Dec. 2000.
9. H. R. Huff, et al., ECS Proceedings, Vol. 2001-09, pp. 263-297, 2001.
10. L. Larson, et al., Solid State Technology, pp. 32-34, January 2002.
11. J. Hutchby, et al., IEEE Circuits and Devices, Vol. 18, pp. 28-41, March 2002.
12. P. M. Zeitzoff, et al., International Journal of High Speed Electronics and Systems, pending publication.
13. SIA 2001 ITRS, op. cit., Emerging Research Devices Section.
Peter M. Zeitzoff received his PhD from Princeton University. He is a senior fellow at International Sematech Inc., 2706 Montopolis Rd., Austin, TX 78741; ph 512/356-3608, fax 512/356-7640, e-mail [email protected].
Robert Murto received his BSEE from Southern Methodist University. He is gate stack thin films program manager at International Sematech Inc.
Howard R. Huff received his PhD from MIT. He is a senior fellow at International Sematech Inc.