Interaction of copper CMP with interconnect integration
07/01/2002
Overview
This paper will discuss three aspects of CMP that interact with module integration: high-/low-selectivity slurries for copper and for the low-k stack, and low-pressure (<2psi) CMP with optimum slurry utilization.
By Malcolm Grief, Jim Schlueter, Saket Chadda, SpeedFam-IPEC Corp., Chandler, Arizona
Successful integration of copper metallization continues to present many challenges to CMP. The manufacture of high-yield, multilevel interconnect structures requires that post-CMP surface topography meets ever more stringent targets. Low surface topography allows dual damascene metallization layers to be formed successfully without being impacted by the topography of the polished surface below. Typical topography-related problems are residual metal remaining in low-lying areas, step coverage, and CD control at lithography.
For CMP, there is a choice between high- and low-selectivity slurries for both the copper and the barrier; these choices are critical and determine the final module results. Currently, the majority of copper CMP processes in production use low-selectivity slurries (LSS) for copper removal, but post-copper CMP dishing and erosion for such slurries are substantial.
Improvement in final topography is typically achieved by the use of barrier slurries that exhibit low selectivity to the underlying dielectric. With such a CMP scheme, a substantial amount of dielectric material (<1000Å) is removed. If exposing the low-k material to the conventional CMP media is undesirable, then this material loss results in the need for thick cap films on top of the low-k dielectric. The total copper thinning of such a process is typically larger than 1000Å. Most fabs in production with these slurries did not have a choice when they were making their respective development decisions, since high-selectivity copper slurries were not available at the time.
Metal thinning or copper loss from the inlaid copper trench is of prime concern to circuit designers, as it increases the resistance of the copper interconnects above what could potentially be achieved. Increasing the dielectric thickness, and thereby the initial trench depth, can sometimes be used as a technique to compensate for high metal thinning, so that the final metal thickness meets specification. This becomes increasingly difficult, however, as aspect ratios of damascene structures become larger. Furthermore, large copper thinning drives up the cost of production due to the increased thickness of the dielectric, the copper deposition, and the increased time of CMP.
The typical CMP process operates at pressures close to 4psi. The industry is projecting the use of porous low-k dielectrics for technology nodes <0.09μm. Porous low-k materials do not have the mechanical strength to withstand high pressures, however, and cohesive failure of porous low-k films occurs when they are exposed to typical CMP pressures. If a conventional CMP process is carried out at low pressures (<2psi), the already low throughput of typical CMP tools drops drastically due to the lower removal rate at lower pressures. As a result, the already high cost of ownership of conventional copper CMP processes skyrockets.
Technology node requirements for various processes have been summarized by the International Technology Roadmap for Semiconductors (ITRS); the latest version for 2001 provides roadmap targets for metal thinning for various metallization levels. Metal layers nearest the silicon surface are defined as local interconnects and have the narrowest linewidths and shallowest trench depths. Intermediate interconnect linewidths are more relaxed and allow slightly deeper trenches. Global interconnects are the upper metal levels and can be designed with larger feature sizes.
High-selectivity copper
As noted above, the combination of conventional copper slurries with a low-selectivity barrier slurry may meet planarity requirements, but is challenged to meet the copper loss targets set by the 0.13μm technology node and below. Abrasive-free copper slurries, however, such as Hitachi Chemicals C430, have been successful on orbital polish tools at achieving very low copper thinning and acceptable final planarity without the need for large oxide loss (metal thinning) [1, 2]. Figure 1 illustrates post-copper CMP (pre-barrier removal) total topography on wafers planarized on an orbital architecture (Momentum) with conventional abrasive slurry vs. abrasive-free slurry. Insensitivity to over-polish for the abrasive-free slurry can be as much as 20x less than for a slurry containing an abrasive.
Use of a high-selectivity slurry (HSS) not only provides good topography (Fig. 1), but also a large over-polish window without causing excessive dishing or erosion. For production environments, this wide over-polish window allows for robust, residue-free CMP. It is clear from Fig. 2 that even a 100% over-polish can occur without causing topography (dishing and erosion) to increase. Electrical resistivity of various linewidths and pattern densities also shows insensitivity to copper over-polish. Therefore, not only is the topography not increasing with copper over-polish, but also, copper thinning does not increase significantly with up to 100% over-polish.
Furthermore, with the low within-wafer-nonuniformity (WIWNU) that is achieved because of the orbital architecture, as well as the through-the-pad slurry delivery, the entire surface of the wafer clears within 3-5 sec, resulting in a tight range of metrics across the wafer and a residue-free surface. Wafers processed in this manner do not have repetitive or topography-related residues as have been reported on a rotary platform [3].
A process using a combination of copper HSS and barrier HSS has been used as a baseline process for dual-level metal (DLM) test lots incorporating both standard and low-k dielectrics with excellent results. Figure 3 is a plot of resistivity measurements of serpentine structures with different linewidths showing the tight distribution of resistivity across the wafer and wafer-to-wafer achieved with such a process.
 Figure 3. Cumulative probability distribution chart of resistivity for different linewidths, using a high-selectivity copper followed by a high-selectivity barrier. |
The use of high-selectivity copper followed by high-selectivity barrier at the first metal and second metal layers on wafers with prior tungsten CMP and high topography has produced mixed results. In many instances, W CMP processes have produced post-CMP erosion of more than 800Å. High erosion from the previous layer is a bigger problem if local interconnect tungsten line structures are present.
Such high levels of incoming topography can cause copper metal residues that cannot be removed by over-polish with ultra-low-thinning Cu CMP processes. This issue can be tackled in two ways. One approach is to improve tungsten CMP performance; orbital architecture has shown process capability at polishing tungsten line and plug structures with resulting dishing of <300Å (Fig. 4).
 Figure 4. Comparison of W CMP erosion for two processes (W2000 and W2585) using orbital architecture. |
Alternatively, a LSS approach for the barrier in conjunction with HSS for copper has been successfully used to meet all the requirements of the 0.13μm technology node. Figure 5 shows the topography on a 100μm structure after copper CMP and after barrier CMP using such a processing scheme. Many barrier slurries now exist that offer the ability to tailor the respective removal rates to process needs.
Extended copper CMP over-polish times can be used to completely remove the copper residues and still achieve the planarity needed to stack further metallization layers without problem. All of this is done while minimizing copper thinning. Combinations of HSS (for copper removal) and LSS (for barrier removal) have been used to polish wafers from M1 through M5 with minimal copper loss and very low topography. Figure 6 is a comparison of resistivity for the three different approaches mentioned above.
 Figure 6. Comparison of resistivity for three different approaches to copper CMP. |
The cost of commercially available abrasive-free slurries is similar to that of conventional slurries. Using abrasive-free slurries, however, requires a higher amount of dilution with hydrogen peroxide as compared to abrasive slurry. For the same flow rate, because of the higher dilution with hydrogen peroxide (significantly cheaper than copper slurry), an abrasive-free process results in a lower cost of consumables. This cost advantage is further amplified by the fact that a smaller amount of slurry is needed with the orbital architecture. Figure 7 shows a plot of removal rate vs. slurry flow rate, enabling choice of the optimum amount of slurry flow.
 Figure 7. Total slurry usage to remove 2μm of copper vs. slurry flow rate and various down forces. (Hitachi AFP slurry, single IC1000 1x1 pad, PDM platen, XDF) |
Low-pressure CMP: low-k
Concurrent with the drive to smaller geometries is the adoption of low- and ultra-low-k (ULK) dielectric materials. These changes present additional burdens on CMP, as many of the currently available ULK materials (k <2.2) are porous and require capping layers to provide a barrier to moisture and contaminates. Because this layer must not be completely removed by CMP and must be as thin as possible to avoid increasing the overall k-value, the use of LSS for a barrier in conjunction with HSS for copper offers a solution.
If CMP is to keep pace with all aspects of the industry roadmap, new process capabilities are needed that reduce copper thinning. Additionally, a byproduct of using materials with a lower dielectric constant is the reduction of mechanical strength. These requirements make the operating pressure window of CMP lower than 2psi. When the pressure of operation is in this range and abrasive-free copper slurries are used, the polish rate drops dramatically to zero when using a rotary platform.
 Figure 8. Removal rate vs. average zone polish pressure using orbital architecture. |
With an orbital architecture, however, reasonable removal rates can be achieved even when operating at low pressures. Figure 8 shows high removal rates (4000Å/min at 2psi) at low pressures.
Some additional benefits of operating below 2psi include less dishing and erosion as the ability of the polish pad to deform is reduced — particularly over large-area features. A reduction in the polishing stress at low pressures benefits the structurally weaker ULK dielectric stacks, thereby ensuring that cohesive failures of the structurally weak films do not occur. Consideration needs to be paid to the adhesion strengths of different films in the stack, as well as to the film quality at the edges of the wafers to ensure that cracks do not originate at the edges and that they do not propagate through the entire wafer, causing delamination.
Conclusion
The evolution of interconnect integration for technology nodes <0.09μm creates significant challenges for the CMP process. Careful selection of CMP consumables, hardware, and the process window allow for these hurdles to be overcome without the need for using risky, unproven technology.
Acknowledgments
Momentum is a registered trademark of SpeedFam-IPEC.
References
1. M.Grief, D.Trojan, K.Murella, "Process Characterization of Copper Polishing Using Abrasive Free Slurry on Orbital and Rotational Platforms," CMP-MIC, pp. 231-234, 2001.
2. M. Grief, S. Basak, T. Battal, F. Mitchel, "The Use of Slurry Distribution Control on an Orbital Polisher for Improved Copper CMP Uniformity and Reduced CoO," CAMP 6th International CMP Symposium, 2001.
3. S. Li, L. Sun, S. Tsai, F.Q. Liu, L. Chen, "A Low Cost and Residue-free Copper CMP Process with Low Dishing, Erosion, and Oxide Loss," Proceedings of the International Interconnect Technology Conference, pp. 137-139, 2001.
Malcolm Grief received his BSc degree in material science from the University of Manchester, England. He has been affiliated with Motorola, Micron, and Philips Electronics, and holds 10 semiconductor patents. Grief is CMP Group process integration manager at SpeedFam-IPEC.
Jim Schlueter received BS degrees in microbiology and medical technology from South Dakota State University, and worked at International Sematech, where he held a variety of positions, including member of the multilevel metals program technical staff. He is director of the metals group (CMP) at Speedfam-IPEC.
Saket Chadda received his bachelor of technology degree in chemical engineering from the Institute of Technology at Banaras Hindu University, Varanasi, India, and his master of science and doctoral degrees in chemical engineering from the University of New Mexico. He has held various positions at Atmel, OnTrak Systems, and Philips Semiconductor. Chadda is vice president and chief technical officer at SpeedFam-IPEC, 305 North 54th St., Chandler, AZ 85226; ph 480/705-4040, fax 425/963-6774, e-mail [email protected].