Computer modeling reveals better advanced gettering methods
07/01/2002
By Andrei A. Istratov, Eicke R. Weber, University of California, Berkeley, California
Walter Huber, Sumitomo Sitix, Fremont, California
Overview
Lower processing temperatures, stricter metal contamination requirements, and rapid thermal processing for advanced IC manufacturing renders some traditional gettering techniques inefficient. Since devices often provide more efficient traps for metals than gettering sites, metal concentrations in device areas may exceed the average dissolved metal concentration by several orders of magnitude. Computer modeling of gettering has evaluated several well-established techniques, as well as ones for future requirements.
Initial studies of gettering by computer modeling [1-3] were confined to simple structures: a gettering layer with a high density of trapping sites and a gettered layer with low defect density. This can describe the behavior of metals in wafers during anneals before doping; often a >3x improvement in gettering efficiency can be achieved by optimizing the cooling rate of these wafers [1, 4].
To our knowledge, these previous studies do not address in detail gettering in wafers containing devices and subjected to a sequence of heat treatments in rapid thermal processing (RTP) equipment with fast heating and cooling rates. Because temperatures, anneal times, and cooling rates are optimized by process engineers to obtain optimum device performance, the structure of gettering sites in wafers should be fine-tuned to achieve the best possible gettering efficiency in existing processes.
We believe our work is the first application of computer modeling to optimize gettering efficiency in wafers during IC fabrication.
Competitive gettering
Conventional gettering reduces the concentration of metal impurities in thin near-surface layers on wafers where devices are fabricated, trapping the impurities at sinks in bulk silicon or at the backs of wafers [5, 6]. Gettering is a means to minimize the detrimental impact of accidental contamination on a production line, thus ensuring reproducibly high yields. This definition implies that gettering should remove metals irrespective of the type and physical structure of devices being fabricated.
Roughly half of all metal contaminants are introduced from the front of the wafer. For these, a gettering layer must have stronger trapping and segregation properties than devices being fabricated. We can neglect gettering properties of simple bipolar devices, such as p-n junctions with ~1016 cm-3 doping. However, more advanced device technologies often incorporate doping up to 1020 cm-3. These heavily doped areas have the same or better segregation properties as heavily doped substrates (i.e., gettering). In addition, strong lattice strains and residual implantation damage in device areas can result in relaxation gettering (i.e., precipitation) of metal impurities by IC devices (see "Relaxation and segregation gettering" on page 96).
We doubt that a gettering technique can be developed that can completely remove metals from the device layer in silicon. A better approach provides a gettering strategy which acknowledges that advanced IC devices are highly competitive as traps for metals.
Iron in silicon
Working on modeling of iron (Fe) in silicon, we confined our modeling to a realistic average 1011 cm-3 metal contamination level (initially homogeneously distributed) and used typical advanced logic device sizes. We assumed the thickness of the device layer is determined by a 100-200nm-deep source-drain contact region and ~50% of this layer's volume is p+ or n+ doped up to 1020 cm-3. To assess the impact of the doping level in the device layer, we assumed that gettering by devices is described by segregation in a 100nm thin p+ layer, doped to 1018, 1019, or 1020 cm-3. For simplicity, we neglected the contribution of residual damage from ion implantation in device areas and out-diffusion of Fe to the wafer surface.
Our "homogeneous distribution" assumption above comes from experiments that show neither segregation nor relaxation gettering of Fe is efficient at high temperatures. Relaxation gettering becomes efficient when equilibrium solid solubility of Fe drops below dissolved Fe concentration (1011 cm-3), whereas the onset of segregation gettering is typically observed from 700-800°C [7-9].
The segregation coefficient of Fe was calculated using published equations and data [7-9]. Gettering modeling was performed for a constant cooling rate from the temperature of 1000 to 200°C using a simulator program [1, 10] developed at the University of California for SiWEDS [11].
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Figure 1. Computer modeling of gettering by p+ 1019 cm-3 (0.008Ω x cm) wafers with 4μm of 1.5 x 1015 (10 Ω x cm) silicon epitaxy, using three device doping levels: 1018 cm-3 blue data points, 1019 cm-3 red, and 1020 cm-3 black. Dotted lines show modeling if devices are the only traps. The following assumptions were used: wafer thickness 725μm, cooling from 200°C to 1000°C at a constant cooling rate, no gettering at 1000°C, and all Fe is initially distributed homogeneously.
Consider the efficiency of p/p+ gettering for different cooling regimes. Figure 1 gives modeled residual Fe concentrations in three device-layer doping levels (i.e., 1018, 1019, and 1020 cm-3) after cooling with various rates (i.e., 0.001°C/sec to 800°C/sec). Here, dotted lines represent Fe concentrations that would accumulate in the 100nm device area if devices were the only traps; these lie at much higher concentrations than the initial 1011 cm-3. Without gettering, Fe in the device layer would jump from 1011 cm-3 at high temperature up to 7x1013 cm-3 by the end of cooling even after a quench at 800°C/sec. This increase is explained by a small thickness of the device layer. For instance, an increase in Fe concentration by a factor of 10 in the device layer is achieved by diffusion of metals from only the first 1μm of silicon — a distance which Fe can diffuse in about 1msec at 1000°C.
Symbols and solid lines in Fig. 1 indicate that gettering by p+ substrates can substantially reduce metal concentration in the device layer. Actual improvement depends on the substrate's cooling rate and doping level. As the doping level of the substrate is close to that of devices, a small variation in substrate resistivity may have a drastic effect on the efficiency of gettering. If the average doping level of devices exceeds the doping level of the substrate (black data points in Fig. 1) by a factor of 10, the metal concentration in the device layer increases to 1012-1013 cm-3. In contrast, if the doping level of the device area is 10x lower than the substrate doping level, the metal concentration in the device layer can be decreased to 109 cm-3.
An important conclusion of our simulations is that a reasonably high efficiency of gettering can be achieved at rapid cooling rates characteristic for RTP. In fact, fast cooling rates can help decrease metal concentration in the device area when it is doped more than the substrate. Overall, a relatively small improvement in substrate resistivity can have a surprisingly strong impact on metal concentration in the device area and hence on device yields.
Our modeling data in Fig. 2 shows the efficiency of internal gettering for 1018, 1019, and 1020 cm-3 device doping levels. These data show that a slower cooling rate achieved a higher internal gettering efficiency. Within cooling rates typical for RTP, internal gettering can reduce device area metal concentration only if oxygen precipitate density is sufficiently high, such as a bulk microdefect density of 1011 cm-3 (Fig. 2b). A lower density of large oxide precipitates (e.g., 109 cm-3, Fig. 2a) has no impact on residual metal concentration after RTP cooling rates.
This is easy to understand because relaxation gettering occurs only below a temperature where metals become supersaturated (e.g., 640°C for 1011 cm-3 Fe). Diffusion coefficients of transition metals decrease exponentially with decreasing temperature [11], so fast cooling rates inherent in RTP treatments significantly limit the distance a metal can diffuse during cooling. It is necessary thus to provide a sufficiently high density of trapping sites for Fe and bring these trapping sites as close as possible to devices to achieve efficient gettering.
Our modeling does show (Fig. 2) that internal gettering can be efficient even with RTP treatments. Cooling rates in RTP systems usually decay exponentially with temperature: initial cooling to 500-600°C is very fast (100-150°C/sec) then cooling to ~200°C takes ~2-3 minutes. Most internal gettering occurs in the temperature range <600°C, where cooling rate is moderately fast. The size and density of internal gettering sites should be optimized, however. A wafer that provides sufficient gettering in conventional furnace processing may not getter well with RTP.
 Figure 3. Simulated efficiency of backside gettering. Graph descriptions same as Fig. 1. |
Fe diffuses ~5μm in 1 min at 300°C, which is a good measure of the distance a metal can diffuse during cooling in an RTP system. A gettering technique optimized for RTP treatments should bring gettering sites at least this close to devices. In contrast, gettering techniques in which metals have to diffuse tens to hundreds of microns to get to gettering sites (e.g., backside gettering, Fig. 3) are inefficient. Unfortunately, quantitative parameters that describe the efficiency and kinetics of backside gettering techniques (e.g., backside damage, polyback, or Al gettering) are lacking, and even the involved gettering mechanism (relaxation or segregation) is uncertain.
To make our modeling of backside gettering generic and to show the impact on the gettering efficiency of large distances between gettering sites and devices, we assumed that a generic 2μm-thick backside gettering layer possesses the best properties that can be achieved in bulk silicon. Its gettering properties are equivalent to those of 1019 cm-3 boron p+ silicon combined with an internal gettering layer with 1012 cm-3 gettering sites and an average precipitation radius of 2.5x10-6 cm. Our simulated results showed that backside gettering becomes competitive with devices and reduces trapped metal concentration in the device layer only at very slow cooling rates (Fig. 3) because it takes Fe >1.5 hrs to diffuse through a 200mm wafer at 640°C, where it becomes supersaturated. At the RTP cooling rates, backside gettering has no effect on Fe concentration in the device area.
Backside gettering may be quite efficient in improving device yield if a significant amount of contaminants are coming from the backside of the wafer, trapping impurities as they diffuse. Such trapping may be a valuable addition to other gettering techniques. In addition, backside gettering may be selectively efficient in gettering fast-diffusing transition metals, such as copper, cobalt or nickel (e.g., Cu can diffuse through a 200mm wafer at 640°C in 45 sec).
Ramifications
Our modeling presented indicates that both internal and p/p+ gettering techniques can be efficiently used in fabricating next-generation ICs, where conventional furnace anneals will be substituted with RTP with faster ramp-up and cool-down rates; this can be done while dealing with ever-lower metal contamination levels. Optimization of gettering becomes paramount, however, since we cannot assume that metals will be automatically gettered by any type of site.
Without efficient gettering, device areas will experience increased metal contamination levels by several orders of magnitudes, compared to the background contamination. Since most 3d metals are gettered only during cooling and can diffuse only a few microns at RTP cooling rates, a high density of gettering sites and proximity to devices is crucial for gettering efficiency.
Very low average metal contamination levels on an IC production line enable one to consider new gettering techniques not feasible at high metal concentrations. Low metal concentrations enable one to consider atomic-size techniques where each trapping site captures a single metal atom [6]. For example, nitrogen doping of CZ wafers, which is thought to reduce density of large vacancy clusters by creating a higher density of smaller (and therefore less critical for device yield) defects, may create a high density of microscopic gettering sites. This represents a completely new approach to gettering. Instead of removing metals from the vicinity of the devices, it provides efficient traps for metals everywhere in the wafer, "freezing in" the homogeneous distribution of metals reached at high temperatures.
Because trapping of metals at gettering sites is weak and gettered metals can be easily redissolved with sufficiently high temperature [13, 14], subsequent anneals can erase a wafer's gettering history. Only the last gettering step is significant if there are no devices on a wafer. With devices present, each gettering step becomes important even if gettered impurities are completely dissolved in subsequent steps.
A surface contamination of 1010 cm-2 alone would contaminate devices up to 1015 cm-3 if all metals from the front wafer surface were trapped in a 0.1μm-thick device layer. High-temperature anneals facilitate diffusion of front surface contaminants deeper than the device layer. Consequently, a large portion of newly introduced surface contaminants can be trapped by gettering sites. Therefore, high-temperature anneals not only erase gettering history, but help establish a homogeneous distribution of impurities, which, as our example showed, often corresponds to the lowest possible metal concentration in the device area.
The suggestion that metal concentration at devices may exceed their average bulk concentration by several orders of magnitude without affecting device yield may at first glance appear to contradict conventional wisdom about device performance. Bear in mind, however, that heavily doped areas of devices have nearly metallic properties that cannot be significantly affected by 1012 to 1015 cm-3 of metals. Metals become detrimental only when they agglomerate in weakly doped areas or form precipitates that penetrate through boundaries between areas with different doping levels. Since the volume of n+ and p+ areas is very small, their gettering ability is limited. High metal-contamination levels eventually result in device gettering saturation, contamination of MOSFET channels, gate oxides, p-n junctions, and degradation of device yield.
On the other hand, as long as metal concentration is low, gettering of metals by p+ or n+ areas helps to reduce metal concentration in critical device areas, improving their parameters. Thus, heavily doped areas of devices already provide a proximity gettering mechanism that reduces device sensitivity to contaminants. Gettering by intentionally introduced gettering sites helps to reduce total metal concentration in a device area, thereby reducing the risk of supersaturation of the device gettering and degradation of devices.
Conclusion
The concentration of impurities trapped at devices can significantly exceed their average concentration in a wafer. This has important implications for the evaluation of metal contamination levels critical for device yield and makes much more meaningful the extremely low dissolved metal concentrations that were found to be detrimental for device properties. The increasingly high sensitivity to metal contaminants of each new generation of IC devices is partly explained by a strong gettering capability of devices themselves. The smaller the device and the higher its doping level, the greater the fraction of total dissolved metals collected by the device. Therefore, yield degradation observed on wafers with an average metal concentration of 1011 cm-3 means actual metal concentration in a device area can be as high as 1012 to 1014 cm-3.
Trapping of metal impurities via devices, combined with fast RTP cooling rates, requires the optimization of gettering to achieve efficiency, but competitive gettering by devices must be taken into account. A high density of gettering sites and their proximity to devices are keys to achieving high gettering performance. Trapping metals by atomic-size defects may become a valid gettering technique.
References
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Andrei Istratov received his PhD in solid state physics from St.Petersburg State University, Russia. He is a scientist at the University of California, LBNL, MS 62-203, 1 Cyclotron Rd., Berkeley, CA 94720; ph 510/486-6634, fax 510/486-4995, [email protected].
Eicke Weber received his PhD in physics from the University of Cologne, Germany. He is a professor of materials science at the Department of Materials Science and Engineering, U. of California.
Walter Huber received his PhD and MSc in solid state physics from the U. of Linz, Austria. He is the director of technology at Sumitomo Sitix Silicon Inc.
Relaxation and segregation gettering
Relaxation gettering is precipitation of supersaturated impurities at intentionally introduced precipitation sites. To achieve effective relaxation gettering, one has to create a high density of lattice defects (e.g., oxide precipitates) in the gettering layer. A faster precipitation of metals in areas with a higher density of precipitation sites [15] than in the gettering layer creates a concentration gradient between them and stimulates diffusion of impurities to gettering sites [16]. Relaxation gettering occurs only when impurities are supersaturated and is kinetically limited by the diffusion of impurities to the sinks.
Segregation gettering is driven by a difference in solubility of metals in two adjacent layers of a wafer; for example, between the weakly doped and heavily doped areas of an epi-wafer, or between crystalline and liquid phases during crystal growth. Segregation gettering is an equilibrium process, i.e., it does not require a metal be supersaturated. Segregation gettering is usually described by the segregation coefficient, equal to the ratio of metal concentrations in the gettered and gettering regions.
Therefore, "negligible" segregation is described by the segregation coefficient S=1, whereas strong segregation would correspond to S of ~10-3 to 10-5.
Although one has to understand the differences between these two gettering mechanisms to model and optimize gettering, it is often difficult to separate the contributions of relaxation and segregation mechanisms in real-life gettering processes. It was initially thought that the contribution of segregation gettering can be separated by annealing a wafer at a high temperature, where the contaminants are not supersaturated and no relaxation gettering occurs, terminated by a rapid quench to room temperature. Recent studies revealed, however, that the segregation coefficient for most metal impurities in p/p+ wafers is temperature dependent, being almost negligible at high temperatures and increasingly significant as the wafer is cooled down. This dependence was observed for Fe and manganese [8-10], and was predicted for copper [17]. Although future studies may prove otherwise, no transition metal was found so far to have strong segregation in p/p+ epi-wafers at high temperature. Therefore, it is an experimental fact that similarly to the relaxation gettering, segregation gettering occurs mainly during cooling the wafer.