Diverse markets require advances in metal etch
07/01/2002
By Michelle M. Bourke, David J. Thomas, Kevin Powell, Yiping Song
Trikon Technologies Inc., Newport, Gwent, United Kingdom
Overview
In today's technical arena of increasing device speeds, low-k materials, and Cu electroplating, it is easy to overlook the classical metals that have been the mainstay of device manufacturing for the last 30 years. Subtractive etch schemes are still an integral part of the great majority of Si-based devices sold worldwide — each device requiring at least one step that etches an interconnect of Al alloy. In this article, we describe some alternate chemistries and etch techniques for high-aspect-ratio features and other device requirements.
According to the ITRS roadmap, DRAM manufacturers will demand subtractive metal etch until about 2008, while advanced logic devices such as microprocessors and fast SRAMs move toward copper damascene processes. To meet this challenge, semiconductor equipment manufacturers need to continue their research to cope with the high-aspect-ratio features required for DRAM at the100nm and 70nm technology nodes.
This forward-looking view of the industry tends to distort the activities of the great majority of Si fabs. Aside from the advanced technology groups, there are also many fabs working on wafers smaller than 200mm. If we consider the total theoretical wafer capacity of worldwide Si fabs, approximately 70% are on smaller substrates. Generically, these wafer fabs operating on smaller substrates tend to work on larger technology nodes. All Al metallization tends to be used at and above 0.5μm features, but W plugs become prevalent below 0.5μm.
Dry metal etching has become one of today's standard requirements for device fabrication. A small percentage of 100-150mm wafers are still wet etched, but this number is diminishing as their technology is developing. The sheer breadth of devices nowadays means that metal etch processes themselves need to be considerably more diverse, adaptable, and extendible than ever before. For example, substrates can range from Si, to silicon-on-insulator (SOI), to quartz and LiTaO3; thicknesses range between 0.15 and 10μm. Dielectrics can be either oxides or nitrides, and barriers/liners are TiW, TiN or Ti. Metal schemes can be Al plug plus Al line (>0.5μm), or W plug plus Al line (<0.5μm). Alloys can vary up to 1% for Si, or up to 4% for Cu, or be as little as 0.5% for Ti.
Not only are vendors learning to cope with high-aspect-ratio etches, they are developing the flexibility to etch a range of materials and layer thicknesses. DRAM devices at the 130nm technology node (ITRS 2001) have a local wiring pitch of 260nm with an aspect ratio of up to 2:1. Power devices, although generally having larger features, typically use thick metal layers — up to 10μm in some instances — with aspect ratios of 3:1. Other devices demand the ability to etch thin metal layers of approximately 300Å, but on pyroelectric substrates. All these variations make metal etching a demanding process.
Metal etch processes are dominated by the use of high-density plasma tools. Such tools use two RF generators. One is used to produce a low-pressure, high-density plasma, while the second controls the ion events occurring at the wafer. This allows a degree of freedom unavailable from the medium density plasmas based on conventional reactive ion etching. In turn, the etch rate and profile may be carefully controlled while maintaining selectivities to both the resist and underlying substrate.
Aluminum interconnect
Aluminum alloy etching remains one of the most challenging techniques due to the range of alloy materials that have been adopted together with a variety of antireflective coating (ARC) and barrier layers. Fundamentals of the approach remain standard, but the specific processes need to be tuned for the layer structure in question. For example, fine tuning may involve different chemistries for different materials, or selecting an appropriate bias power for the copper content of the alloy.
 Figure 1. Cross section of a typical interconnect layer structure. |
Figure 1 is a typical schematic of an interconnect cross section. Si (~1%) is added to prevent junction spiking and Cu (0.5-4%) to increase electromigration resistance.
At grain boundaries and interfaces, there is a tendency for the alloy constituents to segregate, which can result in post-etch residues. With the volatility of Si and Cu byproducts lower than for Al, a more physical process is required to remove them or post-etch residues may result (Fig. 2a). Increasing the bias power helps to make the process more physical but with the trade-off that selectivities to resist and oxide are reduced. To achieve a maximum selectivity to resist, a higher HBr flow is beneficial. Increasing the HBr flow, however, gives rise to an increase in post-etch residues (Fig. 3).
 Figure 3. Increasing the amount of HBr improves the selectivity to resist. |
By selecting the bias power to balance the needs of residue removal and high selectivities, and possibly with the use of multistep recipes, a residue-free etch with smooth sidewalls and high selectivities can be achieved (Fig. 4).
 Figure 4. Effects of HBr on a) resist selectivity and b) residue. |
Etch chemistry
The majority of metal etching today uses chlorine as the main process gas, where the etching of Al is primarily chemical once the native oxide has been removed. To break through the native oxide, a level of ion bombardment is required.
 Figure 5. Mechanism for sidewall blocking during metal etching. |
Once breakthrough has been achieved, ion assistance from the bias power helps in controlling the rate and directionality of the process. To prevent the process from being isotropic, the sidewall of the feature must be protected. Sidewall blocking in metal etch processing is achieved through the formation of a CxCly polymer that originates from the etching of the resist mask with Cl2 (Fig. 5). This sidewall blocking is also critical in preventing localized undercutting of the ARC and barrier materials (Fig. 6).
 Figure 6. Examples of a) sidewall pitting and b) mask undercut as a result of insufficient sidewall polymer. |
By adding BCl3, heavier ions are formed in the plasma that are more effective at removing the less volatile alloy and also help to remove native oxide. This is at the expense of lower selectivities, however. As BCl3 is a heavy liquid at room temperature, it can also be a problematic material to control through the system hardware.
When using Cl2 alone, a selectivity to photoresist of ~1.5-2:1 is typical, but it is effective in removing etch residues and improving corrosion resistance. As devices shrink, resists become thinner, yet metal thicknesses remain similar, so this selectivity to resist is not acceptable as critical dimension (CD) loss becomes a problem.
 Figure 7. Effect of HBr on Al and resist etch rates. |
An approach that we have been successful in adopting is the use of HBr as an additive to the Cl2 plasma. HBr tends to block the photoresist and oxide sites, thus reducing their etch rates. The introduction of HBr also improves the Al etch rate as the number of Cl2 radicals increases (Fig. 7). The combined effects improve the overall selectivity of the process. By increasing the amount of HBr present, the selectivity to resist improves, enabling the etching of higher-aspect-ratio features.
In practice, a combination of Cl2 and Cl2/HBr chemistries are often chosen for a multistep process. The table is a trend chart showing how the various parameters affect the etching of Al alloys. For example, to increase the aluminum etch rate, increasing the Cl2 flow will have the biggest effect, whereas altering the platen temperature has no effect.
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Corrosion prevention
In dry etching of Al metal, it is important that all chlorine residues be removed while the wafer is still under vacuum. If the wafer is vented before this, the moisture reacts with the Cl to form HCl and this, in turn, corrodes the Al through the formation of aluminum hydroxide.
Curiously, the removal of the Cl involves forming volatile HCl and then pumping it away. An approach we use involves heating the wafer. Plasma containing O2 and NH3 is used to remove both the photoresist and Cl residues. A wet DI water rinse to ensure that all of the Cl is flushed away is not necessary with this approach.
As the Cl-impregnated materials also contain traces of the etched metal, the wafers must then go through a wet solvent treatment. Most fabs demand that etch processes have a tolerable delay before this wet strip can take place — 48 hr are typically required.
Applications
The ITRS road map indicates that the ability to etch small, high-aspect-ratio features will be required until about 2008. As linewidths continue to shrink, the capabilities of photolithography become the main constraint. To resolve smaller linewidths, thinner resists are being used in combination with complex ARC layers. This helps preserve the CD of the feature and allows resists to be thinner.
The use of HBr has helped in etching smaller features down to 0.2μm as the resist selectivity is higher. Unlike other approaches, selectivities to resist greater than 5:1 have been seen. From the table it can be seen that, in addition to improving selectivity, the introduction of HBr also improves the Al etch rate, feature profile control, selectivity to substrate, and CD control of the process. The highly selective approach also allows for wafer topography and greater metal thicknesses (Fig. 8).
 Figure 8. Other benefits of high resist selectivity include a) extendibility to 120nm and the ability to cope b) with topography and c) with thick metal. |
For many etch vendors, a maximum of 2% Cu in the alloy is the upper limit. At Trikon, Al alloys with up to 4% Cu have been successfully etched with a residue-free etch surface and smooth sidewall (Fig. 9). Here, it is better to sacrifice resist selectivity by using Cl2 only, which is more effective at removing the Cu residues than Cl2/HBr.
 Figure 9. AlCu (4%) interconnect. |
Metal etching is currently finding its way into non-IC manufacturing. For example, surface acoustic wave (SAW) devices are fabricated on pyroelectric substrates particularly prone to electrostatic charging when the temperature is varied. If these materials are allowed to discharge uncontrollably, this may lead to device damage or, in extremes, wafer breakage. Therefore, additional aspects of the process must be carefully controlled. Particular attention needs to be paid to the wafer temperature during etching, the anticorrosion process, and system venting.
Electrostatic clamping is routinely used to control the wafer temperature during metal etching. The electrostatic chuck used in the process can accommodate insulating substrates such as SOI and quartz, allowing for diversification into new market segments such as SAW and displays.
Conclusion
Today's 100-200mm fabs require at least one metal etch step and will for some time to come; metal etch processes require the flexibility to cope with an increasing diversity of needs.
This article has focused on the need for simple, controllable metal etch processes. In particular, the advantages of a Cl2/HBr approach have been discussed. Such processes are easily adapted to meet the challenges of the ITRS Roadmap, the changing needs for Si processing, and even emerging requirements such as those for SAW filters.
Michelle Bourke graduated from Heriot-Watt University with an honors degree in optoelectronics and laser engineering, and was a research scientist for the Defense Evaluation and Research Agency in Malvern, UK. She is technical marketing engineer for etch products at Trikon Technologies Inc., Ringland Way, Newport, Gwent NP18 2TA, UK; ph 44 1633 474592, e-mail [email protected].
Dave Thomas received his BSc in chemistry at Leeds University, and his MSc in surface chemistry and PhD in chemistry at the University of Bristol. He has held positions at the University of Southampton and Nortel Networks. Thomas is etch product marketing manager at Trikon Technologies.
Kevin Powell received his first-class honors degree in physics from Bristol University and joined Plessey Semiconductors as a process engineer. He also held positions at Qudos Ltd. and National Semiconductor. Powell is etch process manager at Trikon Technologies.
Yiping Song received his BSc in physics from Beijing Normal University and his PhD in semiconductor physics from the University of Ghent. He conducted research on thin film properties at Durham University and on plasma etch at the University of Bristol and Glasgow before joining Electrotech Ltd. in 1995. Song is a principal engineer at Trikon Technologies.