Solutions for maximizing die yield at 0.13μm
07/01/2002
By John Ferguson, Mentor Graphics Inc.,
Andrew J. Moore, TSMC Inc.
Overview
Unlike traditional design rule checks, which have a clear pass or fail definition, yield issues are dependent on a number of variables and are more difficult to pin down. Chip and wafer planarity, metal and oxide adhesion, and electrical charge effects can have a major impact on total chip yield. By identifying trouble spots and implementing a "cure," it may be possible to achieve a yield greater than that created by simply meeting the design rules and guidelines. For example, rather than placing diodes arbitrarily — even if consistent with design rules — better yield can result if parasitic effects are considered when placing them.
Maximum yield is an important goal of companies making products from integrated circuits. For most manufacturing processes, yield issue identification appears in design rules or guidelines. The problem with yield, defined as the ratio of working chips to total chips manufactured, is how to maximize it without also increasing manufacturing costs. Foundries such as Taiwan Semiconductor Manufacturing Corp. (TSMC) are working to ensure high yield for their customers. As designs grow more complex, processes become smaller, and geometries increase, the work required to achieve acceptable yield becomes increasingly demanding. With consideration of the issues and prior planning at the design rule checks (DRC) level, however, complications can be reduced and yield enhanced.
Identifying planarity
Planarity — the difference in oxide heights for a given region on a design — is an important factor affecting wafer yield. When a design has regions of low metal density, the oxide layer can sag considerably. Polishing does help improve planarity, but if metal density is particularly low, the amount of oxide sagging can be too great to overcome.
To correct planarity, it is first necessary to identify where low-density regions occur. Historically, DRC tools are used to scan the full chip for a binary pass or fail. This is useful only as a sanity check, providing little or no information on how to source or fix a planarity problem. A better solution to locating low-density regions is to use the DRC tool to scan the chip in smaller increments, defined by a window of a specified dimension, and stepped across the chip by a given increment (Fig. 1).
 Figure 1. Outputs from stepped window. Planarity check using DRC tool stepped across chip in a given increment and isolated error output. |
There is a trade-off with the stepped approach: a great deal of data must be redundantly checked, adding more time to the operation. This is easily outweighed by the reduction in time required to fix the problem.
Solving planarity with metal fill
Once the low-density regions are identified, they must be repaired. The most common approach is to insert additional metal, not for electrical purposes, but simply to help keep the planarity constant. There are three generally accepted methods of creating this metal fill. The most tedious way is to insert it by hand through a layout editor; this is time-consuming and error prone. A second approach is to use automatic insertion methods in layout or place-and-route tools. Although this approach is certainly faster and easier, grid restrictions and other issues often limit the amount of metal fill that can be placed.
A third and recommended approach is to do automatic metal fill insertion at the time of physical verification. This simplifies the task because density checking and repair can be done in a single iteration. Mentor Graphics' Calibre physical verification tool uses a single command to automatically generate rectangular metal polygons that can be placed in identified low-density regions. More complex, nonrectangular geometries can also be processed, although more rigorous coding is required (Fig. 2).
 Figure 2. Metal fill in low-density region; automatic planarity repair. a) Before: identified low-density region; and b) after: corrected with automatic fill patterns. |
Since planarity is a full-chip problem, the added metal fill is often created in a flat manner, increasing the amount of data in the design database. If the inserted metal fill is created in a regular pattern, however, the increased data problem may be greatly reduced if the DRC tool recognizes the patterns and outputs the data as a standard GDSII array reference. Calibre DRC has the ability to recognize such structures intuitively, whether created by Calibre automatically or by other external means. By doing so, the amount of data expansion after metal fill insertion can usually be kept to ≤10%.
When inserting metal fill, regardless of the method used to create it, the influence on design timing must be considered. If the metal fill is left "floating," it can affect the timing and signal integrity of neighboring signal lines. These effects are often difficult to identify since standard simulators cannot account for floating components.
The alternative to floating metal fill is to tie all inserted metal fill objects to ground, but not every piece of metal fill will have a means to do so. As a result, this solution naturally reduces the total amount of planarity repair that can be accomplished. In order to properly tie the metal fill, more vias, contacts, and intermediate metal layers must be used. This method significantly increases the expansion on the total design database and can have detrimental effects on timing, because more parasitic capacitors are created. This method may also affect the integrity of the ground plane.
The impact of inserting metal fill for planarity repair on timing and signal integrity has not been fully explored and is not completely understood. It is important, however, for designers to consider all possible ramifications.
Metal slotting: Rectangle vs. square
Another factor affecting yield is metal slotting. Many physical reasons make including holes or slots in the metal desirable. For aluminum processes, metal slotting can help avert electromigration; for copper processes, metal slotting gives the copper something to "stick" to, which helps offset the sagging effect. Each process has a preferred method of metal slotting.
In general, there are two accepted types of holes, or slots, that are used in metal slotting. The first, most commonly associated with aluminum processes, involves the creation of rectangular slots. The second type, most commonly associated with copper processes, involves the insertion of simple square holes. This method is commonly referred to as "Swiss cheesing."
With rectangular metal slotting, constraints must be taken into account. To minimize current blockage, slots must be aligned in the same direction as the current and staggered to allow a freer channel of electron flow. Problems occur at "T" junctions or similar structures where divining the current flow becomes tedious. Rounding the junctions (corners) creates slots that are no longer pure rectangles, making them more difficult to implement. DRC tools do not have a concept of current direction, so they cannot provide a complete solution. However, debug time may be saved by automatically slotting in appropriate areas and implementing metal slotting by hand in those areas that cannot be easily automated.
Because of the additional constraints on this type of metal slotting, there are many associated design rules that must be followed. The biggest hurdle in checking that a slot meets the design rule constraints is in properly identifying the slot from any other hole that might exist in a metal structure, a potentially time-consuming process. By far, the easiest way to address this problem — and as a benefit, dramatically reduce DRC runtimes — is to create the metal slots on a separate layer. Using this approach automatically eliminates the extra work required to identify slots and the created slots can be quickly checked for compliance with various dimension requirements.
By contrast, the creation of square slots (Swiss cheese) is much less burdensome. A square is equal in vertical and horizontal dimensions. Thus, the orientation of the slot will not impede current flow as a rectangular slot does, nor will it require unique configurations around corners.
TSMC has created Calibre rules to automatically generate the square slots required for copper processes. While the RECTANGLES command already allowed Calibre to generate rectangular polygons in a specified region, the capability was used mainly for metal fill. TSMC's experience with the syntax and knowledge of the requirements for copper slotting enabled an internal need to be filled: the automatic slotting in copper.
Obviously, metal slotting involves a challenging design issue. Although some layout-related tools offer methods to automatically slot wide metals upon creation, they often have limitations. Furthermore, slotting wide metal lines by hand is time-consuming and error prone. Metal slotting, like metal fill insertion, can be easy to implement at the physical verification stage using a DRC engine, especially in the less constrained case of square slots. Employing the same algorithms used in metal fill insertion, Calibre can place automatic slots in wide copper lines.
Antenna effects
A third problem that can affect chip yield is antenna effects. During chip processing, interconnect components are subject to charge accumulation. If the amount of charge collected on these conductor lines is sufficient, it may significantly damage or even destroy a transistor gate. Identifying antenna failures requires a sufficient modeling technology based on the processing physics involved. To properly identify and repair possible antenna occurrences, it is important to understand the characteristics of the areas of possible charge in standard aluminum, copper, and via processing methods.
In aluminum processing, an ion etch is used to remove excess metal underneath a masking layer, allowing for the accumulation of charge along the sidewalls of the metal. Once excess metal is removed, the mask layer is removed with yet another ion etch. This creates a charge that accumulates along the top of the metal line.
Once the metal layer is fully processed and an oxide layer is built on top of it, all the charge that had been associated with the metal will seek a means to dissipate. As a result, antenna effects come into play at the time of fabrication for each metal layer.
Properly modeling this type of antenna requires calculating both the area of the metal (proportional to the charge accumulation on the top of the line) and the perimeter of the metal (associated with the sidewall charge accumulation of the line); calculating the cumulative transistor gate area; and, modeling the sequencing of each metal line fabrication.
In copper processing, previously created trenches are filled with copper. The only etch required is to remove excess copper from the top. As a result, only the area of the metal line must be calculated for modeling purposes. Charge associated with a layer will dissipate prior to processing the next layer. Consequently, a model that properly considers the available connectivity paths at each processing step is still required.
Another important situation to model when considering antennas is the often-overlooked case of charge accumulation during via creation. When a via is created, oxide is etched down to the metal below. At this point, charge can accumulate on the lower metal proportional to the area of the via and needs to be taken into account to get a comprehensive representation of the electrical effects on chips during manufacturing.
 Figure 3. Reverse-biased diode. A reverse-biased diode is capable of draining a significant amount of charge. |
The presence of diodes must also be considered when modeling the antenna effect (Fig. 3). At high temperatures, such as those used during IC fabrication, a reverse-biased diode is capable of draining a significant amount of charge. (In normal conditions, these high temperatures are not reached; diodes will not impact the signals significantly, other than occasional timing effects due to added parasitic capacitances.) When attached to an antenna, the amount of charge available is greatly reduced. It is important to note that this does not apply only to specifically designed diodes. At this point in manufacturing, any standard np junction can act as a diode, including source and drain regions.
The amount of charge that a diode can drain depends on its strength and can be modeled by the total diode area along an electrical net. It should not be assumed, however, that any diode has sufficient strength to drain the charge from a large antenna.
Proper identification of antenna effects is required to model connectivity based on sequential processing and to calculate the areas and perimeters of various components, including gates, diodes and the interconnect layer itself.
Fixing antenna violations
There are two commonly accepted procedures for correcting antenna violations: additional diode insertion and metal jumpers. Diode insertion presents a number of difficulties. The most obvious problem is in finding a suitable place along an antenna net to place a diode. Although it is often not modeled in standard DRC antenna checks, there are parasitic effects that should be considered when placing a diode. The ideal place for a diode would be beside the transistor gate or gates that are in the greatest danger of failure, but identifying these gates requires an entirely different antenna model. Charge naturally follows the path of least resistance. If a diode is not placed intelligently, the accumulated charge may break a weak gate rather than travel a highly resistive path to a diode elsewhere on the net.
Another problem in placing diodes is calculating the total diode area required for a given antenna. Placing a single diode does not guarantee that transistors along a net are truly safe from antenna effects. The total diode strength required on the net must also be known. This makes placement of a diode or multiple diodes even more difficult (Fig. 4).
Protection diodes can also affect timing. A diode placement requires, at a minimum, the addition of a contact to an existing line, and may also include the creation of net metal and via placements. Although these should not dramatically affect the timing on the signal, they do add to the parasitic effects on any neighboring metals.
For these reasons, an automated approach to correcting antennas through diode insertion is extremely difficult, if not impossible. The time required to iteratively identify antennas, make repair attempts, and reverify the net is far too lengthy and does not provide sufficient repairs when completed.
The second method of repairing antenna violations is through metal jumpers. Because charge associated with a layer will be eliminated by the time the next interconnect layer is processed, breaking a long line and going up or down a layer through vias makes it possible to split the total charge to the transistors in jeopardy. This can greatly alleviate the damage to each transistor, but this approach also requires special considerations.
First, it requires adding vias along a line, increasing the resistivity of the net and increasing the timing of the signal. Second, the placement of a metal jumper along a line is not arbitrary. The location must be carefully considered to ensure that the total change in the charge characteristics to each portion of the metal line being repaired is known (Fig. 5).
Because automated methods have serious drawbacks, the best solution for repairing antenna violations is by hand, and the best way to ensure the fastest and most accurate manual implementation is with useful and essential information. Calibre has the ability to output (and highlight in the layout) each layer identified as an antenna on a net-by-net basis. This information can be broken down further to identify all the connectivity layers existing along the electrical net to that point. Each layer will contain information on its area, perimeter, or polygon count based on the antenna model used. With this information, it becomes simpler to correct an antenna violation by hand in a layout environment.
Using diodes to help solve antenna problems, TSMC has discovered that it was necessary to check the total area of the diode against the amount of charge modeled by the antenna itself. Together with Mentor Graphics, TSMC found an algorithm that enabled this check process to be accomplished accurately and rapidly. The result was a new Calibre SVRF rule syntax that checks the ratios of antennas with no path, to a diode and antennas with paths, to diodes using a single command.
Conclusion
No production line can provide 100% working chips on a silicon run. Although yield issues are difficult to tackle, designers can help ensure optimal yield by carefully considering the types of issues that can affect total yield. Designers can also work with companies that address and incorporate these issues in their products and processes. Adopting foundry rules that address yield may be more complicated for the designers, but the end result will be increased yield and profitability. In using the Calibre system for verification sign-off and having regularly scheduled meetings with its supplier, Mentor Graphics, TSMC has improved yield by discussing accuracy and performance issues with respect to rules files.
John Ferguson received his PhD in physics from McGill University in 1991, his MS in applied physics from the University of Massachusetts in 1993, and his PhD degree in electrical engineering from the Oregon Graduate Institute of Science and Technology in 2000. He is a technical marketing engineer with Mentor Graphics Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97070-7777; ph 503/685-7000, [email protected].
Andrew Moore received his BSEE degree from the University of Illinois and PhD from Caltech. In 2000, he joined TSMC, where he is design services marketing manager, specifically focusing on EDA services and relations. He has held various positions at Mentor Graphics, Xerox PARC, and Tanner Research.