MRS spring fling: Organics, nanowires, CMP

06/01/2002

by Debra Vogler, SST Senior Technical Editor

Beginning a presentation at MRS' Spring Conference with a photo of rat bone tissue may seem a bit unorthodox, but Paul Calvert, professor of materials science and engineering at the University of Arizona, did have a point. Scientists are searching for new ways of toughening ceramics and composites, and a material that mimics bone tissue is also needed for medical implants.

"Biological growth is a layer-by-layer process where cells work together, rather like an inkjet printer, in expressing solidifiable material," explains Calvert.

Calvert went on to present results obtained using inkjet printing — with highly modified HP printers — to build organic electronic devices and/or structures. He maintains that inkjet methods can be used in many more formats than simply printing single layers of a passive ink. For multilayer printing, the problem is ensuring that new layers of ink don't mix with previous layers.

The issue becomes how to chemically solidify the previous layers, which Calvert suggests could be done by using thermal or photo-crosslinking, or by codepositing two reactive inks. Subsequent printing can be carried out using either thermal or piezoelectric print heads. Due to his efforts to print and immobilize dielectrics, metallic conductors, and polymer gels, Calvert achieved a resolution of 50μm, adequate for many display applications.

Organic thin-film transistors
A topic that comes closer to traditional semiconductor manufacturing is that of organic thin-film transistors (OTFTs). Because processing of OTFTs can be done at low temperatures, they can be deposited on a wide variety of material, such as polymeric substrates, cloth, paper, etc. As Thomas Jackson, professor of electrical engineering at Penn State, put it: OTFTs enable electronics anywhere — and the performance of the best OTFTs is now rivaling, and in some cases exceeding, that of amorphous silicon devices.

Jackson also presented comparison data between two different types of OTFTs, showing that napthacene OTFTs had mobility about one order of magnitude less than pentacene OTFTs, but napthacene circuits were slightly faster (~25%). The threshold voltage and subthreshold slope of the napthacene devices offered some circuit advantage over pentacene devices. Jackson believes the pentacene devices can be modified to gain the advantages of napthacene and have substantially better performance.

Progress aside, the field of OTFTs is still in its infancy. Taking these devices to the next level — the manufacturing floor — will need additional work. An example of a relatively high-priced, high-margin product incorporating OTFTs is a flexible, polymeric substrate display. However, questions remain about device stability, reliability and reproducibility, according to Jackson.

"But the best-demonstrated results are comparable to, or better than, hydrogenated amorphous silicon devices—the most commonly used transistor technology for direct view flat panel active matrix liquid crystal displays," notes Jackson. "This needs a manufacturer to decide there is money to be made to make the investment needed to move to manufacturing."

Low-price/very low price/low-margin products could include electronic bar code tags (e.g., RF ID tags), smart cards, and sensors for food quality. "For products of this type, pieces other than organic transistors also need substantial work," states Jackson.

Being able to do the patterning at very low cost, with improved resolution and reduced defect density, will be the major challenge.

FlexICs is trying to bring manufacturing considerations to bear in the area of organic light-emitting devices (OLED) display backplanes on flexible substrates. Several challenges the company faces in using plastic substrates include not exceeding a process temperature of 100°C, and accounting for thermal expansion and shrinkage.

Nanotechnology
Another concept covered by a number of presentations at the conference involves nanowires, which could be used for such future applications as nanoscale electronic and photonic devices. While commercial applications belong to the future, the well-known vapor-liquid-solid crystal growth mechanism — used many years ago to grow whiskers — is now used by Peidong Yang, assistant professor of chemistry at the University of California, Berkeley, to construct nanowires. Made in this manner, nanowires are defect-free, according to Yang, unlike typical ICs with multilayer thin films.

"For our superlattice nanowire, we can get around the problem [of lattice mismatched materials] by relieving the lattice strain laterally," comments Yang.

CMP challenges
A common theme at the symposium was finding solutions to the complexities introduced to CMP by shallow trench isolation (STI) and the introduction of copper dual-damascene to multilevel interconnects, such as nanotechnology and hard mask materials.

Nanometer height variations on the order of 20-50nm that occur on millimeter lateral length scales in virgin silicon wafers are the origin of nanotopography issues. These areas of variation interact with the CMP process, causing substantial localized thinning of surface films, e.g., oxides or nitrides, used in STI. Duane Boning, assistant professor in the department of electrical engineering and computer science at MIT, presented data from a joint project with BayTech Group and ADE Corp.

In particular, Boning compared three models — scaling, filtering, and contact wear — with respect to two issues: failure to clear oxide and excessive nitride thinning. When oxide is not cleared because the nanotopographical variations weren't taken into account while determining the polishing endpoint, the result is incomplete transistor formation, leading to device failure. If one tries to solve the problem by increasing the overpolish time—which affects the entire wafer, not just the areas of nanotopography—then areas that are lower in height will have excessive nitride loss, causing transistor performance degradation.

The scaling model was described as a statistical aggregate approach based on the work of Schmolke, in which a transfer coefficient is correlated with final oxide thinning. The contact wear model is based on the numerical simulation of pad elastic properties, which results in a complete map of oxide thicknesses that is then correlated to the known nanotopographical surface.

The filtering model is a signal-processing method that captures the spatial smoothing done by CMP. When applied to known (pre-measured) nanotopography maps, it predicts final oxide thicknesses. The research team discovered that the scaling model does not capture localized spatial interactions; the best results were obtained using the contact wear model; the filtering model was somewhere in between.

The challenges of STI were also jointly addressed by IMEC and Sandia National Labs. Representing Sandia, David Stein, senior member of the technical staff in the microelectronics development laboratory, noted that the scaling of STI is fraught with major difficulties associated with trench etch into silicon (corner rounding), high-aspect-ratio trenches (damage to trench corners), and planarization (pattern layout effects).

The complexity of addressing these issues can perhaps best be seen by taking a closer look at the problem of pattern layout effects (i.e., material removal over areas of the circuit with a high density of underlying features occurs more slowly than in areas with a low density of underlying features). Stein presented three methods that could be used to address the problem: dummy structures, oxide reverse etch, and dual nitride. But there is no easy answer to the question: "Which one is best?"

While dummy structures are the most widely used to help avoid dishing and erosion effects, Stein notes that the integration scheme of the total STI module and the design of the part being produced have to be taken into account.

Still another CMP challenge in the wake of copper dual-damascene used in multilevel interconnects is being able to remove the stacks of Cu overburden and liner layers. Wei-Tsu Tseng, advisory scientist at IBM's Semiconductor R&D Center, discussed results of studies using hydrogenated silicon nitride and hydrogenated silicon carbide as hard mask materials. For CMP of multilayer structures, the IBM team found that polish rate depends on the mechanical properties of the underlying layer.

Advances in process technology almost always lead to the need for change in metrology and the use of exotic materials for low- and high-k dielectrics, as well as gate dielectrics, is no exception. X-ray reflectivity (XRR) was presented by Christine Russell, applications scientist at Bede Scientific, as a quick, nondestructive tool for examining these new materials.

"In the case of high-k dielectrics, layer thickness is crucial to the next generation of gate dielectrics," notes Russell. "TEM [transmission electron microscopy] requires the destruction of the sample, but XRR can be used in a fab line as a process control tool." The company has already deployed XRR tools in fabs.