For DRAM and logic: CVD low-k dielectric integration
06/01/2002
by Keith Buchanan, Trikon Technologies Ltd., Newport, UK
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Overview: Issues associated with the integration of CVD low-k dielectrics for 100nm technology node applications are described, including key film properties and factors determining successful integration into advanced DRAM and logic interconnect schemes.
Advanced dynamic random access memory (DRAM), logic, and system-on-chip (SOC) manufacturers are increasingly using low-k dielectric materials to reduce parasitic capacitances in device interconnects [1, 2]. Use of CVD processing offers an evolutionary approach to the introduction of low-k intermetal dielectrics (IMDs) with a transition from plasma enhanced CVD (PECVD) SiO2 (k>4) to so-called organo-silicate glass (OSG) materials (k<3).
For DRAM applications, aluminum-tungsten metallization is likely to extend to the 130nm technology node and possibly further [3]. Here, low-k dielectrics must be integrated into a subtractive metallization scheme, and the very tight pitches demand that the dielectric deposition process have excellent gap-filling capability. In conjunction, zero overlay design rules and unlanded vias make low-k integration more challenging. The projected k value range for a 100nm DRAM interconnect is 2.5-3.0, providing an ideal application for CVD OSG low-k materials with gap-filling capability.
For DRAM applications, aluminum-tungsten metallization is likely to extend to the 130nm technology node and possibly further [3]. Here, low-k dielectrics must be integrated into a subtractive metallization scheme, and the very tight pitches demand that the dielectric deposition process have excellent gap-filling capability. In conjunction, zero overlay design rules and unlanded vias make low-k integration more challenging. The projected k value range for a 100nm DRAM interconnect is 2.5-3.0, providing an ideal application for CVD OSG low-k materials with gap-filling capability.
In logic applications, low-k dielectrics are used both with conventional aluminum-tungsten interconnect and copper metallization in damascene architectures. The ITRS 100nm technology node demands a k value <2.2, which implies that porous materials be used. Such materials can be somewhat difficult to integrate, particularly in dual damascene applications where multilayer dielectric stacks must be deposited and patterned on up to eight metal levels. Cu diffusion barrier layers must be incorporated and carefully engineered to give good barrier performance with minimal increase to the effective k value. Likewise, materials and interfaces must ensure interconnect reliability.
Al-W integration
Trikon's low-k IMD process for gap-fill applications offers a k value of between 2.4 and 2.9. Its essential properties are shown in Table 1. The result of this process is a methyl-doped organo-silicate formed from the reaction of hydrogen peroxide and methyl-silane at low temperature. The low temperature deposition ensures that condensation at the wafer surface drives gap-fill and the k value is tuned by careful optimization of the deposition and cure parameters. The deposition and cure, together with under- and over-capping layers, are deposited in the same cluster tool.
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Via etch and strip processes may need to be re-optimized when low-k materials are introduced into the interconnect scheme. low-k organo-silicates typically have a lower oxygen and higher carbon content than standard PECVD oxides. This compositional difference can cause excess polymer formation that can significantly reduce the via etch rate, or even cause etch stop. Consequently, the polymer-forming constituents of the etch gases should be reduced to compensate for the material properties.
Via strip over the low-k material is re-optimized, typically by moving away from a fully oxidizing chemistry. Fourier transform infrared (FTIR) spectroscopy is a useful tool for monitoring the effects of etch and stripping processes on the low-k material, since compositional changes will be reflected by changes in the FTIR spectra. Integration of the peak intensities allows quantitative comparisons to be made, and thus significant material degradation can be measured.
Alongside FTIR, measurement of dielectric constant stability over time is also useful, since a degraded film will typically absorb moisture and the dielectric constant will increase over time.
The challenge of low-k integration increases significantly when zero overlay design rules are used. Here, unlanded vias are inevitable because of lithography alignment tolerances. Consequently, even in fully embedded schemes where the low-k material does not extend above the metal lines, the via etch will extend into the low-k material.
Any subsequent outgassing from the via during PVD liner or tungsten plug deposition can degrade the plugging process, leading to so called "via poisoning" [7]. With some spin-on materials, this poisoning can be sufficiently problematic to prevent the use of zero overlay integration schemes.
 Figure 1. TEM cross-section of unlanded vias and via chain resistance distributions: a) zero overlay with no misalignment; b) misaligned by 45nm. |
Figure 1 shows a cross-sectional transmission electron microscope (TEM) of low-k Flowfill (k = 2.8) successfully integrated into 0.13μm interconnect. Tight distributions of via chain resistance are obtained for both aligned and misaligned cases. In the scheme shown, the low-k layer is not restricted to the regions between the metal lines (nonembedded low-k integration).
Low-k CVD for damascene
Logic interconnect, with its greater complexity and number of wiring levels compared to DRAM, demands the use of copper wiring for low resistance and low-k for minimal parasitic capacitance from the interconnect. Here, dielectric constant values <2.2 are needed for 0.1μm technology, limiting the available candidate materials.
 Figure 2. Reported values of dielectric constant vs. density. |
It is instructive to look at the relationship between dielectric constant and density. Figure 2 shows reported values of dielectric constant vs. film density for a variety of both spin-on and CVD SiO-based low-k materials, together with a PECVD SiO2 reference. A strong correlation is seen, suggesting that, for this group of materials, the reduction in dielectric constant is achieved principally through density reduction.
For fluoro-silicate glass (FSG) films, data for which [4] is also plotted in Fig. 2, the relationship between dielectric constant and density is different, suggesting that another factor is influencing the value of dielectric constant. Fluorine is known to be electro-negative and will reduce the polarizability of the material; so, for a given density, it has a lower k value. There is a limit to the amount of fluorine that can be added to SiO2 while maintaining film stability, however. FSG films have minimum useful k values of around 3.6. For OSG films having k values of around 3.0, it is suggested that carbon doping disrupts the silica network, thereby producing a more open structure and lower density.
A family of CVD low-k dielectrics for damascene applications offers carbon-doped OSG films with k values as low as 2.0. These films have dielectric constant vs. density characteristics consistent with the relationship shown in Fig. 2.
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Key properties of these ultralow-k films are shown in Table 2. A comparison of both families of films (Table 1 vs. Table 2) shows the carbon contents to be similar. The significantly lower k values of the damascene films must, therefore, be achieved through means other than carbon doping. Cross-sectional TEM analysis shows that the damascene films are porous and the pore diameter is estimated as 1-4nm. Such porosity has previously been associated only with spin-on dielectrics, demonstrating the potential extendibility of CVD films to 100nm processing and below.
Thermal desorption spectroscopy (TDS) and atmospheric ambient stress hysteresis measurements show the proprietary low-k dielectric films to be thermally stable to 500°C. Additionally, the dielectric constant does not change significantly with either a 500°C anneal in nitrogen or 24-hour water immersion. These films also adhere well to all materials commonly encountered in dual damascene interconnect stacks (Ta, TaN, SiC:H, SiN). Adhesion is measured on blanket depositions and after a 450°C anneal using the procedures detailed in ASTM D 3359-97 [5].
Damascene stack properties
Use of a CVD cluster tool allows the integration of dual damascene stack processing on a single tool. For dual damascene applications, incoming wafers are first plasma-cleaned in a reducing ambient (gas mixtures containing hydrogen) to remove native copper oxides and CMP residues. The damascene stack — barrier layer, low k for via and line, plus etch stop layer and hard mask if required — is then deposited in situ.
 Figure 3. Metal line height reduction with technology node. |
Material properties of the etch stop and hardmask layers become increasingly important with successive technology generations. Figure 3 shows the trend in metal line thickness reduction as predicted by the ITRS. At the 100nm technology node, both local and intermediate interconnect lines are <500nm thick. As dielectrics in the damascene stacks become thinner, the effects of etch stop and hardmask layers on the effective dielectric constant (keff) become more significant. This is shown in Fig. 4 where keff is plotted against etch stop/hardmask thickness and dielectric constant. The total stack thickness is 400nm and the low-k material has a dielectric constant of 2.0. These simple calculations exclude electrical field fringing effects, but the trends shown are valid.
 Figure 4. Effective dielectric constant (keff) vs. etch stop and hard-mask layer thickness and dielectric constant. |
The data in Fig. 4 show that etch-stop materials such as silicon nitride (k≈8) increase keff too much to make them practically useful; this has been previously reported [6]. For a line thickness of 400nm, however, even silicon carbide (k≈4.5) increases the effective dielectric constant >30%. To limit the increase in keff to <10%, the etch stop and hard mask must have an inherently low-k value (~3.0) and be thin (<40nm). Production of films with such qualities is one of the major challenges facing semiconductor fabrication equipment and process suppliers.
Damascene integration
The integration scheme demonstrated for the CVD low-k dielectric films (described above) in a single damascene interconnect is shown in Table 3. The silicon carbide and Orion films are deposited in the same CVD cluster tool. The silicon carbide (SiC:H) etch stop and hard-mask are compressively stressed, and this lowers the overall stack stress, the Orion film itself being in tension. At lithography, 0.18μm line/space trench blocks can be printed directly onto the low-k material using standard 248nm equipment and materials.
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Although a hard-mask is included in the process flow described above, this was included as a CMP stopping layer, and it is not needed to prevent resist "footing." The trenches are etched using CF4/CH2F2 chemistry for both the antireflective coating and the low-k dielectric film. The etch produces straight, smooth sidewalls with no observable bowing as judged from scanning electron microscope (SEM) cross-sections. Selectivities to photoresist and to the silicon carbide etch stop are 4:1 and 5:1, respectively.
Resist was stripped in the etch tool using a reducing chemistry, and the process was optimized using FTIR spectroscopy and k value measurements to ensure no degradation of the low-k dielectric film. A proprietary, low-k-specific chemistry (EKC 640) was used to remove post-etch polymers, although work is under way to eliminate the need for this step by using plasma for both resist strip and polymer clean.
 Figure 5. Cross-sectional SEM images of etched trenches: a) after trench etch/strip and Ta deposition; b) after copper plate and CMP. |
Metal copper diffusion barrier and copper seed were deposited using conventional (ionized) PVD techniques. Trench fill by copper electroplate and subsequent copper CMP were done using industry standard equipment, although no attempt was made to optimize the processes. Figure 5 shows cross-sectional SEM images of etched trenches with Ta barrier deposition and of the completed structures following copper CMP.
Because the copper CMP process had not been optimized, there was significant over-polish and more than 100nm of the CVD low-k dielectric film was removed. Despite this, there is no observable physical or chemical degradation of the film. FTIR spectra taken after copper CMP and compared to blanket film data show no significant differences.
 Figure 6. FTIR integrated peak ratios from blanket Orion film and from single damascene wafer after copper CMP. |
Figure 6 shows integrated peak intensities from FTIR spectra with the data being referenced to the principal (Si-O-Si) peak. Spectra taken from patterned and unpatterned areas of the wafer after copper CMP show minimal change in peak intensity, indicating no film degradation.
Conclusion
CVD dielectric films for both aluminum-tungsten and copper damascene interconnect architectures at the 100nm technology node have been described. Key film properties of a family of CVD low-k dielectrics are tabulated together with data demonstrating integration of the CVD films. These proprietary films offer carbon-doped OSG films with k values as low as 2.0, addressing ITRS 100nm node IMD requirements.
Acknowledgments
Flowfill and Orion are registered trademarks of Trikon Technologies Ltd.
References
1. W. Li, G. Sandhu, Advanced Metallization Conference 1998, pp. 499-505.
2. R.D. Goldblatt, et al., Proc. International Interconnect Technology Conference (IITC) 2000, pp. 261-263.
3. International Technology Roadmap for Semiconductors (ITRS) 2000 Update; Interconnect.
4. Lim, Shimogaki, Nakano, Tada & Komiyama J. Electrochem Soc; 146 (11) 4196-4202, 1999.
5. ASTM D3359-97. Standard methods for measuring adhesion by tape test.
6. P. Xu, K. Huang, et al., Proc. International Interconnect Technology Conference (IITC) 1999, pp. 109-111.
7. K. Ikeda, T. Hasegawa, et al., Proc. International Interconnect Technology Conference (IITC) 2000, pp. 158-160.
Keith Buchanan is process integration manager at Trikon Technologies Ltd., Newport, Gwent, UK; ph 44/1633-414025, fax 44/1633-414180, e-mail [email protected].