Manufacturing at k1 = 0.2 with chromeless phase lithography
06/01/2002
Overview
Reticle structures comprising properly spaced pairs of chromeless phase edges with 100% transmission regions between can project very fine circuit images using high-numerical-aperture exposure tools equipped with off-axis illumination. A hybrid system with more opaque regions can print a wide variety of circuit features.
Phase-shifting mask (PSM) technology that can take advantage of high-numerical-aperture (NA) exposure tools — in combination with off-axis illumination (OAI) — can extend optical lithography to enable very low-k1 manufacturing. Socha and Chen separately reported the use of high-transmission attenuated PSM (attPSM), which shows very promising potential for patterning both poly gate masks and contact masks [1, 2]. In contrast to alternating PSM (altPSM), attPSM is intrinsically a three-beam imager; this makes it suitable for use in conjunction with off-axis illumination to convert critical patterns to two-beam behavior, further enhancing printing performance.
The relative magnitude of the diffraction components projected by attPSM varies with the transmission of the attenuating material: The 0th order gets weaker while the 1st-order component becomes stronger when transmission is increased. This observation correlates well with the finding that higher-transmission attPSMs produce a wider process window. With "100% transmission" PSM — essentially a chromeless PSM — one can push imaging to 0.2k1 or below when combined with both high-NA (>0.7) and strong OAI.
Chromeless phase lithography
The 100% transmission attPSM is conceptually very similar to today's 6% attPSM. For example, a poly gate mask (clear field) will have phase-shifting areas on the mask that define the desired poly regions. The chromeless phase lithography (CPL) mask can be made by etching the quartz substrate of a conventional chrome-on-glass reticle blank to create π-phase depth after the initial chrome patterning. The chrome is then removed in subsequent steps to reveal non-phase-shifting areas. Both "π-phase background areas" and "0-phase patterning areas" share the same quartz substrate and, in theory, they both allow the exposure wavelength to pass through fully.
CPL should not be confused with the chromeless single phase-edge PSM that has been studied by many in the past [3]. Dark CPL aerial images are always formed by two phase edges in close proximity. The image formation is intrinsically symmetrical with no unwanted phase-edge images. Except for variations in OPC strategy, the CPL layout needed to form a resist pattern on the wafer is not substantially different from that of a traditional binary chrome mask. CPL is intended to be a single-mask technique.
Figure 1 plots a family of nine aerial images formed by two separated phase edges at different spacing on a KrF scanner with 0.8NA and 0.85σ. The largest phase-edge separation was 300nm. The others were in order: 250, 200, 150, 100, 80, 60, 50, and 30nm (all at 1x wafer scale). When two phase edges are separated by 300nm or more (black), there is minimal interaction. Since each phase edge independently casts a "shadow," two separate line resist patterns would be formed on positive resist.
As the phase-edge separation decreases, the interaction becomes more apparent. The magnitude of the center intensity peak begins to diminish due to proximity interaction. When the separation is 150nm (the brown or fourth curve from the outside), the two phase edges join and form a wide, single, aerial image. As we move the two phase edges closer, we observe that the proximity interaction has caused the center peak to have an intensity inversion. At 100nm separation, it is now a single aerial image and the minimum intensity (Imin) is much "darker" than the individual aerial images that are formed by an individual phase edge at 0.85s. For a positive resist system, a darker aerial image is highly desirable, since it allows printing finer resolution patterns using high exposure energies.
Based on the above simulations, the best linewidth range for CPL (or 100% attPSM) is likely to be in the range of 0.16-0.32(λ/NA). For 0.8NA KrF exposure, CPL can thus be used for resist linewidths from 50-100nm. With ArF or F2 exposure systems, this system has the potential to print minimum line features with widths down to 40 and 30nm, respectively! Due to the strong optical proximity effect from paired phase edges, we expect that for >0.32k1 imaging, CPL will not offer great benefits over conventional chrome-on-glass masks. Hence, clever mask design is needed for large features.
Optimizing CPL for best imaging performance
Both NA and illumination require some optimization for CPL technology. Figure 2 shows a family of aerial images formed by an 80nm (1x) line at 300nm pitch corresponding to a series of NA settings. At the dark line location, the sequence of NA settings (from the least dark) is: 0.50, 0.55, 0.60, 0.65, 0.70, 0.75, 0.80, 0.85, and 0.90. We see that the higher NA settings produce steeper aerial image slopes, greater image modulation, lower Imin, and better contrast.
At the traditional intensity threshold (Ith) of 0.30, the aerial image width varies with NA. This development threshold would require a substantial amount of mask negative bias to print the desired 80nm linewidth on the wafer with a lower NA system (NA<0.60) [4]. The aerial image "iso-width" occurs near Ith = 0.20, corresponding to slight overexposure and to the actual mask feature edge. Correct sizing at slight overexposure is a strong technical benefit when using a positive resist system, since the overexposure regime tends to be more forgiving of mask error factor, and it may be relatively easier to achieve the desired CD uniformity.
The image profile also depends on partial coherence (σ) and, of course, defocus. Unlike the case of strong phase-shifting masks, CPL imaging is better at higher s. At Ith = 0.2, the aerial image width is a function of partial coherence with higher σ closely reproducing the intended linewidth and lower values oversizing the dark line. However, there is little difference for σ>0.5.
Figure 3 illustrates that further performance can be achieved using the Quasar type of quadrupole OAI. The CPL linewidth is 80nm at a pitch of 280nm with KrF exposure and 0.8NA. The black and blue lines are aerial images from Quasar illumination (σout = 0.85; σinner = 0.55; wedge = 30°) for best focus and 0.25μm defocus settings, respectively. The red and gray are from conventional illumination (σ = 0.9) with the same focus settings. It is clear that Quasar is likely to produce a much better process window with lower Imin and steeper log-slope at Ith = 0.2.
 Figure 4. Experimental wafer results using CPL printed from an ASML /800 KrF. |
Figure 4 shows actual top-down SEM CD data as printed on a wafer by an ASML /800 KrF system with 0.8NA and the same Quasar illumination setting as in Fig. 3. The KrF resist thickness is 330nm on top of inorganic BARC on a bare silicon wafer. The target line CD is 80nm and the line feature pitch is 260nm [5]. The results show that excellent process windows are achievable (12% exposure latitude with DOF > 0.6μm). Thus, CPL produces a manufacturable process margin for dark lines with k1 = 0.26 and kpitch = 0.84.
Shrinking the feature pitch remains one of the major challenges. Shorter exposure wavelengths and even higher NA are two possible options, but those require new exposure tool development. Another option is to make the illumination more aggressive, pushing souter close to the unity limit. Extreme quadrupole or dipole illumination makes it possible to print features with pitch below the exposure wavelength. Simulation suggests that dipole illumination with σouter = 0.95 and σinner = 0.65 and 30° wedge angle should produce a reasonable process window for 50nm CD features with a pitch of 180nm using KrF exposure at 0.8NA. Dipole illumination, however, requires multiple exposures to print realistic 2-D circuit features. Using a 90° Quasar (or c-quad) illumination on an ASML /800 KrF scanner, we have experimentally demonstrated high-fidelity imaging of 90nm resist lines at 1:1 duty factor (i.e., with 180nm pitch) over a 300nm range of focus [6].
CPL mask design application
In Fig. 1, we saw that CPL imaging works best when the feature width (or the separation between the two phase edges) is <0.32(λ/NA). For features that are much larger, it is likely that light will "leak through" between phase edges where pattern areas are intended to be dark. This would be disastrous, but can be prevented by clever mask design. A dark grating design for large pattern areas is one reasonable approach. The idea is to simply create pairs of proximity phase edges to collectively produce a shadow over the large pattern areas. Figure 5 is an example of a) such a design approach with b) a corresponding SEM photo from printed wafers.
 Figure 5. Use of "dark grating" to produce contact landing pads in a two-transistor layout. a) the mask design, and b) a SEM photo from a printed resist wafer. |
Another approach is to use a hybrid CPL that combines both chromeless phase-shifted features and an opaque reticle design on the same mask. Figure 6a decomposes a simple example of a logic circuit design with the poly gate and active area mask regions superimposed. The critical gate features can be identified and extracted as groups of vertical and horizontal line features. This approach allows shrinking the gate features without changing the overall layout design rules. The less-critical features can then be placed in separate layout data layers. The critical gate features will be imaged with CPL. The less-critical features can be either chrome or 6% attPSM. Figure 6b shows the gate features separated from the other less-critical features and recombined in a hybrid CPL mask pattern. More realistic logic designs using hybrid "three-tone" CPL masks will require rule- and model-based OPC for both chromeless and chrome mask features. [7]
This hybrid mask requires two maskwriting and etching steps. This means that the second writing step needs to align to the first. Since this alignment occurs at 4x mask scale, the accuracy requirement is sufficiently tolerant enough that it can be achieved by the current maskmaking process. We propose that this tolerance be no more than 30nm at reticle scale. Once both types of mask features have been defined on the same reticle, a single exposure is necessary for each exposure field during the wafer-scanning/-stepping stage.
Conclusion
In this article, we have introduced a very strong RET candidate that has demonstrated the potential to achieve sub-0.2k1 imaging using off-axis illumination. Assuming that a typical σouter setting for OAI is 0.90, it is feasible to print poly gate mask features with a target CD of 70nm and with the minimum pitch close to 160nm using ArF exposure with 0.85NA (such as ASML's upcoming /1200 system). Our 50nm design node simulation predicts that ~125nm minimum pitch could be achieved with a 0.85NA F2 exposure system when it becomes available.
Since CPL aerial image formation always involves symmetrical pairs of phase edges, it differs significantly from altPSM, where 0 and π phase-shifted edges form the image asymmetrically. Thus far, we have not yet observed a strong 3-D mask topology effect as we would typically expect from altPSM. Making, inspecting, and repairing CPL reticles will be less challenging than for altPSM.
In recent observations [3], we have seen that 2-D optical proximity effects appear to be a much more challenging issue for low-k1 imaging than lens aberration sensitivity. We intend to investigate both phenomena in more detail. Finally, while we expect the industry to relentlessly pursue shorter-wavelength solutions to meet the next-generation design rule requirement, it is also reassuring to know that there is more than one alternative for optical extension technology in existence today that can be readily chosen as a backup strategy in case of unavoidable delays in the new lithography frontier.
Acknowledgments
The authors thank John Petersen, Petersen Advanced Lithography; Robert Socha, ASML Technology Development Center; Judith van Praagh, ASML; and MaskTools' Application Engineering Group led by Stephen Hsu (Xuelong Shi, Michael Hsu, and Linda Yu).
References
1. R.J. Socha et al., SPIE, Vol. 3748, pp. 290-314, 1999.
2. F.C. Chen et al., Microlithography World, 9, pp. 12-20, Summer 2000.
3. F.C. Chen et al., SPIE, Vol. 4346, pp. 515-533, 2001.
4. C. Mack, KTI Microlithography Seminar, Interface '91, pp. 23-35, 1991.
5. We have observed that top-down SEM CD measurements average 10-20nm higher compared to more reliable cross-section SEM CD measurements. Based on our confidence that a CD measurement offset exists, we have corrected the experimental data so that it reflects actual cross-section measurements.
6. D.J. Van Den Broeke et al., SPIE, Vol. 4691, to be published, 2002.
7. R.J. Socha et al., SPIE, Vol. 4691, to be published, 2002.
For further information, contact J. Fung Chen at ASML MaskTools, 4800 Great America Parkway, Ste. 400, Santa Clara, CA 95054; ph 408/855-0503, fax 408/855-0549, e-mail [email protected].
J. Fung Chen, Doug Van Den Broeke, Tom Laidig, Kurt E. Wampler, ASML MaskTools, Santa Clara, California