Reducing costs with wafer-level test and burn-in
06/01/2002
Overview
Integrated device manufacturers continually seek ways to lower costs in every segment of the manufacturing cycle. In particular, reducing the cost of test is a mandate. One technique that holds the promise of significant cost reduction is wafer-level test and burn-in — an accumulation of various testing concepts that reduces the number of process steps associated with electrical test.
by Pat Kiely, Tokyo Electron America, Austin, Texas
The recent definition of wafer-level test and burn-in (WLBT) has its origins in the more limited concept of wafer-level burn-in (WLBI). WLBI was intended to replace the stress test on packaged parts, typically accomplished by an extended heat cycle in an environmental chamber. WLBI was an attempt to achieve the burn-in step on the wafer as soon as it left the fab. High-reliability parts usually undergo burn-in, at least until the statistical data supports a quality level such that infant mortality risk is reduced.
In many cases, the design rules change so quickly that burn-in is never completely eliminated. However, the early design challenges of managing a stable contact on a full wafer, while maintaining planarity and thermal control, were proven in multiple parallel product runs on the test floor [1]. In addition, die disconnect was implemented to prevent damage to the wafer and to the WLBI system from high-current failures.
Once design for testability (DFT) came to the fore, WLBI evolved from burn-in to include testing (i.e., WLBT). DFT begins with the design step; it provides a chip configuration for each die that has built-in self-test (BIST) incorporated into the product design. The die can then test itself with the introduction of an external stimulus signal plus a limited test pattern. Using serial input of the test pattern, BIST reduces the number of signal pads required on each die vs. parallel I/O (input/output), which is common in most full spectrum testing. DFT also enables the reorientation of the contact pads such that they are spaced to accommodate the electrical contactor in the WLBT system. Electrical contact is less expensive if the normal pad pitch of 50μm is effectively expanded to 100μm by designating every other pad for WLBT.
The net result is the reduction in: 1) the number of signal paths, 2) the complexity of the wafer contactor, and 3) the performance specification of the tester. Using DFT concepts, full wafer test and full wafer burn-in have been achieved on product wafers containing 500+ die.
Results have been published that chart the progress made in cooperative programs between integrated device manufacturers (IDMs) and equipment suppliers over the last six years [1, 2]. Many of the technical challenges have been resolved, and in many cases, the original design goals were modified and original targets were shifted as knowledge was acquired. Today, WLBT can be correlated to wafer sort, but the correlation to package test is not complete.
 Figure 1. Typical electrical test flow. |
Electrical testing today
Electrical testing steps vary with the product, but a typical scenario is shown in Fig 1. WLBT is focused on the test applications generally found in wafer sort and assembly/packaging. In the fab, electrical test consists of in-line DC parametric test — usually on test structures in the scribe lines — and end-of-line wafer electrical test (WET) — also a DC parametric test on test structures in the scribe lines. (DC parametric testing has not been a topic of investigation for full wafer test applications due to the variation inherent in the adaptive test mode, plus the typical location of the test structure in the scribe line outside of the product die array.)
Once the wafer gets to the sort floor, wafers are sorted in two steps. In the first step, a Wafer Sort 1 test is performed on the product die to verify performance and mark bad die. After the dice are laser trimmed, as needed, the Wafer Sort 2 test confirms yield improvement from the laser trim step.
At assembly and packaging, either passive burn-in testing (for a time at temperature) is done, or, alternatively, dynamic burn-in testing is done. This testing is where patterns are run with the device at temperature followed by a test for opens/shorts and an at-speed functional test. (The choice is determined either by the product or the IDM's budget. Some products can be heated [passive] simply to weed out infant mortality. Others can be selected by the introduction of external test patterns.)
Considering the number of test steps, the cost of each test cell, and the extended cycle time to deliver a functioning product in the form factor desired by the customer, the motivation to reduce steps, cost, and cycle time is clear. Furthermore, IDMs understand the benefit of moving test results to the earliest part of the production cycle. In a typical manufacturing cycle, the time from wafer start to packaged product is 12 weeks. The ability to determine package yield while the die is still in wafer form offers several advantages: predictive results in 7 rather than 12 weeks; faster feedback to the wafer fab about yield-limiting problems; savings from reduced capital expense; savings by not packaging/testing bad die; and less risk of wafer/die damage due to reduced handling.
The package burn-in step is a prime target for cost reduction. It requires die sockets, burn-in boards, ovens, power supplies, test pattern generators, plus multiple handling steps and extended test times (6-72 hrs). Adding significantly to the total device cost are not only the wide variety of die products and applications, but also the dice/assembly/test costs.
IDMs would like to sell bare die to their customers with a guarantee of quality and performance. These customers then assemble the known good die (KGD) as needed. Many IDMs want to eliminate burn-in, but market requirements for high reliability (e.g., automotive) preclude its elimination, at least in the early phase of the product life cycle.
Another problem is the testing of die to meet "as packaged spec," without the package step. Some market segments (memory, cell phone, controller, etc.) are served by modules rather than packaged die, so there is also a need to deliver KGD with 100% probability that automated assembly of a module will yield a fully functional product.
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The next target for cost savings: getting rid of external test systems and test steps. Several IDMs have developed scenarios with DFT and BIST with a goal of optimizing chip design and embedding test circuitry in the product die. The challenge here is the need to adopt these methods in sync with time-to-market goals and with minimal increase in die area. Finally, there is a concern about limitations on test coverage in the absence of full functional external test systems. An external tester is still required, but early results from a structural tester offer potential savings vs. a traditional functional tester.
Given the advantage of moving test results upstream from the assembly process, there are opportunities for cost savings and cycle shortening by implementing burn-in and test on the wafer. Ideally, the WLBT system will replace at least one wafer sort step and the package burn-in step. Depending on test coverage at WLBT, the final test at package or bare die would be limited to an "opens/shorts" test at greatly reduced cost vs. functional test.
Motorola published results of WLBT on a PowerPC product, demonstrating correlation of WLBT with wafer sort and preliminary data from package burn-in [1]. The product configuration was a bumped wafer with array contacts on the die that contained BIST. The next phase of the project is verification of burn-in on a peripheral aluminum pad die with tighter pitch, with BIST implemented in the third phase. The early results are promising enough to warrant continued development by Motorola and its supplier partners, although IDMs will not publish exact numbers for competitive reasons.
Technical challenges
The obstacles facing IDMs who want to take WLBT beyond its current state are substantial. All of the typical problem elements are present, and some are immensely compounded in the WLBT environment, as described below.
Testing all die on a wafer in parallel generates heat, which can damage already processed wafers, hence the need to control the thermal budget. Depending on product type and number of wafers, it may be necessary to dissipate power in a range from 300W/wafer to 50,000W/wafer. Most WLBT systems will need to manage the power as the die are activated and tested in multiple cycles for extended hours.
Full electrical contact has to be maintained on the wafer for this extended time while all the components (wafer, contactor, interface board, and environmental chamber) are expanding and contracting, depending on the CTE (coefficient of thermal expansion) of each. Repeatable electrical results have been shown up to 1200W/wafer for test and burn-in cycles of 24 hrs at test temperatures controlled at 150°C [1].
Also, as the components expand with increasing temperature, the goal is to keep perfect electrical contact between the interface board, the wafer contactor, and the die pads during the temperature cycling. Ideally, system components in proximity to the wafer will be designed with material that closely matches the CTE of silicon. Consistent results have been attained during electrical testing on 200mm bumped wafers at burn-in temperatures up to 150°C.
Continued development of WLBT requires that materials, corrosion, wear, or any other factor associated with the wafer contactor will not compromise the quality of electrical test results. A compliant contactor that can accommodate any change in planarity across the contact surface from the interface board to the wafer, and to the bottom pressure plate, is needed. The compressive force to achieve contact resistance (Cres) will vary based on wafer, contactor, and contact pad material. Repeatable Cres on 200mm bumped wafers has already been achieved and early experiments with aluminum pad wafers indicate that similar results can be expected.
The WLBT system must be capable of detecting high current, monitored continuously, on every die during the test cycle. The system also has to be capable of disconnecting the out-of-limit die to prevent damage to the system components and damage to adjacent die. This capability has been demonstrated on product wafers (see previous sections) [1].
Wafer design should be optimized to enable access to signal, power, and ground pins on each die with the smallest number of traces on the interface (I/F) board and the wafer contactor. In other words, DFT features have to be an inherent part of the design process. The challenge is to route all the paths within the wafer surface (either 200mm or 300mm) available for die contact. Techniques include designating contact pads in an alternating scheme to reduce the number of contacts needed, and expanding the pad pitch from a typical 50μm to 100μm for an aluminum pad. Today, repeatable results have been achieved on bumped wafers with an effective pitch of 250μm using DFT techniques. Early experiments on aluminum pad wafers indicate that full wafer test can be implemented with an effective pitch of 100μm.
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Test circuitry must be enabled in each die, such that the die can be activated with a minimum number of external stimulus points for signal, power, and ground. In addition, a minimal monitor (output) path is required to reduce the burden of the interface circuitry and contactor. Designs have been shown using <10% of the available contact pads. Patterns are generated serially from the external WLBT test system and test results are sent from the monitor point and stored in the WLBT system. Effective test coverage has been achieved with strong correlation to wafer sort data.
Because WLBT must limit the amount of interconnect from the tester to the die to achieve coverage of all die on the wafer, full spectrum testers are not suited to this application. A structural tester is complementary to the restricted interface to the die and is designed to activate BIST structures at relatively low clock rates. WLBT using an integrated structural tester has demonstrated test coverage and yield results comparable to wafer sort on product wafers [1].
Maturing the WLBT concept requires that the issue of power dissipation be addressed. There is a finite limit to both the number of watts/die and die/wafer, compounded by the burden of extra BIST circuitry on each die, plus the potential increase in leakage current, depending on design and process parameters. As noted above, repeatable results have been achieved at 1200W/wafer. There is no readily apparent solution at power levels of 50,000W/wafer, which may be expected with high-performance processors.
For maximum cost-effectiveness, the WLBT system must be capable of wafer handling, full wafer contact, thermal management, and test pattern generation. Automated wafer handling is a design goal, but today, the system is limited by the variety in contactor technology, which requires custom material handling beyond the scope of some of the current projects. Improved material handling, system automation, and throughput are tasks for the future.
 Fig. 2. Designing WLBT into the process flow. |
For an IDM to attain the maximum benefit from WLBT, the decision to use it must be made early in the design cycle of the target product (Fig. 2). DFT, by definition, is the first step required so that the circuitry and the chip layout accommodate full wafer test. To help support ROI calculations, the WLBT decision should be made before extensive investment is made in traditional test equipment. All the elements presented here should be managed at the start of the initial phase of a new design.
Since validation of WLBT takes a long time, product wafers must be run through the process in parallel with the traditional test/assembly flow. But product wafers are very valuable, and customers are usually waiting for delivery. Therefore, allocation of wafers to the parallel path of WLBT is always a major challenge. Naturally, as the new product design is debugged and validated, changes will be made, further slowing the correlation as new versions are sent through the process. Patience is a key ingredient for success.
Organizational challenges
A major hurdle for implementing WLBT is that IDMs do not know how to evaluate, select, buy, and operate these systems. The concept does not have a history; it is not on an approved tool list; and it crosses organizational boundaries — and some geographic ones — so that a recognized tool owner is not apparent. Table 1 lists some of the organizations and job specialties that should be involved in evaluating the tool. Assuming the tool is ordered and delivered, there must be continuous liaisons through all these groups after the tool is qualified, regardless of which group is the designated owner.
The broad spectrum of engineering specialists required to bring the elements of WLBT together (Table 2) is daunting. It takes a strong leader at the IDM to appoint a team and hold it together during an extended development and evaluation cycle. The equipment supplier needs a leader and strong team as well.
Financial challenges
IDMs have largely ignored R&D investment in evolving integrated solutions such as WLBT, and equipment suppliers are trying to innovate on tight budgets. Also, the WLBT concept cannot be proven with simulations or models; wafers must be available for validation. Furthermore, correlation with the full spectrum of electrical tests in a production environment has to be achieved. Experienced resources are needed to staff such projects.
Inevitably, design changes are required due to new product specs, wafer size, etc. Most suppliers are strained to sustain this kind of herculean effort through all the changes over extended periods without receiving a purchase order. Clearly, investment in staff and production validation by IDMs are also substantial. But, with creative purchase agreements to attract more suppliers and sustain them through the development cycle, it should be possible to break through the barrier to continued development of WLBT.
Conclusion
WLBT has cleared major hurdles with proven results in production and Motorola has demonstrated results on product wafers in a manufacturing line. Although the possibility of using WLBT to eliminate some testing steps and to validate "as packaged" performance remains to be fully realized, current WLBT test results correlate well with wafer probe data and full correlation with package testing will be completed soon. Full versatility across multiple products is the next challenge, and the continuing flow of DFT solutions promises to deliver broader production results in the very near future.
References
1. T. Cooper, G. Flynn, G. Ganesan, R. Nolan, C. Tran, "Demonstration and Deployment of a Test Cost Reduction Strategy Using Design-for-Test (DFT) and Wafer Level Burn-in and Test," Future Fab, Vol. 11, June 29, 2001.
2. D. Conti, J. Van Horn, "Wafer Level Burn-in," IBM Microelectronics Div., 2000 Electronic Components and Technology Conference (IEEE), pp. 815-821.
Pat Kiely received his BA from Rutgers University. He is business unit manager, test systems, at Tokyo Electron America, 2400 Grove Blvd., Austin, TX 78741; ph 512/424-1331, e-mail [email protected].