Some fundamentals of wafer-level packaging
06/01/2002
by Deborah S. Patterson, Kulicke & Soffa, Flip Chip Division, Phoenix, Arizona
Overview
Wafer-level packaging is gaining popularity because it reduces the size of a package to that of the IC itself, and it lowers package costs by allowing the fabrication of the package in a batch process. In addition, WLPs will allow cost to be scaled with die shrinks, since the packaging process is no longer decoupled from the wafer. Being able to package, test, singulate, and ship known good die streamlines handling and shipping logistics, further reducing overall costs and cycle times. The joint consideration of package and semiconductor design will result in efficiencies in device layout that will improve component performance.
A wafer-level package (WLP) and a wafer-level chip-scale package (WL-CSP) are similar terms used to describe the packaging of an active IC or passive component when packaging process steps are carried out while chips are still in wafer form. As with other packaging techniques, a WLP must provide thermal and electrical pathways while ensuring a reasonable level of protection from the environment. Equally important, a WLP must be compatible with standard surface mount technology (SMT) assembly processes.
Devices and applications
Wafer-level packaging is growing at a significant rate. Prismark Partners predicts a 210% CAGR by unit through 2005 [1]. Devices forecast to drive this growth are integrated passive and active circuits, performance memory, and lower lead count components such as flash/EEPROM, high-speed DRAM, SRAM, LCD drivers, rf devices, logic, power/battery management devices, and analog devices (voltage regulators, temperature sensors, controllers, operational and power amplifiers, etc). These devices will support end applications in mobile phones, memory modules, PDAs, notebook PCs, digital video controllers, and telecom networks.
When analyzing whether a semiconductor can be converted to a WLP, device size, the number of bond pads, and desired pitch must be evaluated together to determine if there is sufficient area underneath the device to support all interconnections. This is because wafer-level packaging requires "fan-in" routing as opposed to "fan-out" routing as illustrated in Fig. 1. With fan-in routing, the edge of the IC itself defines the boundary of the wafer-level package.
Like CSPs, wafer-level packages are currently manufactured with SMT-compatible pitches of 0.8mm, 0.75mm, 0.65mm, and 0.5mm. Figure 2 shows these four pitches plotted as a function of device size and I/O count. The graph approximates whether an IC can support a given I/O count as pitch changes from 0.8mm to 0.5mm. The graph provides an approximation because designers can also take advantage of combining compatible I/Os to reduce chip-to-board interconnections. With the emergence of 0.5mm pitch as a new standard (and 0.4mm pitch following), more device types will be able to use wafer-level packaging, since the smaller pitch will support more interconnections.
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WLP technologies
Integrated device manufacturers (IDMs) have introduced WLP for certain products. These companies include: Atmel, Bourns, California Micro Devices, Dallas Semiconductor, Fairchild, Fujitsu, Hitachi, International Rectifier, Maxim, Micron, Mitsubishi, National Semiconductor, NEC, OKI, Philips, STMicroelectronics, Texas Instruments, and Xicor. Several types of WLPs are offered through merchant packaging suppliers and these fall into three basic technology categories (Table 1).
Thin-film redistribution WL-CSP technology is the most popular approach used today due to its lower cost and successful compliance with board-level reliability standards for high-volume, portable applications. Figure 3 shows this type of WLP in an Ericsson Bluetooth Headset and a Handspring Visor Edge handheld computer.
Next-generation technologies and enhancements are in development for higher I/O devices. The reliability requirements of the final application will drive technology adoption. Since thin-film redistribution technology dominates today's markets, we must look at present design and processing considerations with respect to this class of WL-CSP.
Thin-film redistribution WL-CSPs
As with all WLPs, wafers are manufactured with conventional wafer processing. Wafers may even be probed to sort and map electrically good die before they are forwarded to a merchant WLP supplier for services. The device layout must first be assessed to ensure that a new ball-based footprint can be accommodated.
 Figure 4. A redistributed flash memory chip with two rows of wirebonded perimeter I/Os rerouted to a ball grid array. |
When evaluating wafer-level packaging technology for the first time, it is typical for engineers to choose an existing wirebonded device for initial WLP conversion. This strategy offers the fastest path to evaluation and confirmation of the approach. However, wirebonded I/O pads are usually placed too close together to accommodate solder balls and, even if it were possible to place balls on the existing I/Os, the resultant footprint might not be optimized to produce the best reliability.
Redistribution reroutes I/O pads on the surface of a device. Figure 4 illustrates redistribution on a wirebonded flash device. The original bond pads along the two short ends of the flash provide electrical connections to the bump array through traces that are routed from them. In this example, two dielectric layers that sandwich a redistributed metal layer are applied to the surface of the device to change the I/O footprint. After this step, solder balls are added (see Fig. 5a) and the chip becomes a stand-alone WLP.
The drawback to redistributing a wirebond design into a new ball array footprint is that the resulting WLP may not be optimized in terms of design, structure, or cost. Once feasibility is demonstrated, however, such ICs are usually redesigned to eliminate the added redistribution. This situation is understood, and a two-phase qualification program is typically defined. Next-generation changes may include an integration of the redistributed layer within the final metal layers of the die, or a complete redesign that provides for the shortest signal lines for improved performance.
The redesign may require new software tools to complement the new mindset. Redesigned signal, power, and ground lines can provide for a very low-cost structure by eliminating external redistribution processing steps and associated tooling. Comparing the two WLP structures in Fig. 5, we find that the first shows a more complicated thin-film redistribution cross section, while the second illustrates a design that allows for the ball to be placed directly on top of the I/O. In this second example, the WLP is defined by the addition of a single layer of polymer material (BCB) that planarizes the wafer, provides protection, and standardizes the surface finish. The latter approach is one of the more cost-effective designs for a thin-film redistributed WLP.
An exception to redesigning a device into a non-redistributed structure is if the device is offered in both a WLP and a wirebonded package. In this case, the addition of a redistributed layer will still be necessary, since the decision on package type may not be made until after wafers are fabricated.
The final structure of a WLP depends on the requirements of the IC and its application. For example, the design for a high-performance memory device may require that a WLP comply with an overall capacitance specification. In this case, to keep the added capacitance of the final interconnect structure as low as possible, it may be necessary to place the bump on top of the redistributed dielectric layer, or the structure may need to use a material with a lower dielectric constant. In a second example, the routing within a final metal layer may be extremely dense and fall below minimum design rules that are needed to create a reliable final structure. The packaging manufacturer may then recommend additional dielectric layers to stabilize the structure.
Today, there exist as many interconnect schemes as there are product types due to the novelty of the approach and to the lack of internal and industry design standards. This will require the IDM and the packaging manufacturer to work closely together and understand each other's specifications and design rules to create the most effective cost-performance structure.
WLP manufacturing considerations
Solder-ball pitch and diameter. Solder joint reliability is influenced by solder volume because increased joint height and diameter extend thermal fatigue life. Typical solder ball diameters measure 0.5mm for ICs having 0.75-0.8mm pitches. Similarly, the solder ball size may decrease to 0.30-0.35mm as pitch approaches 0.5mm. Preformed solder spheres are typically used for these constructions. Solder joints that measure ≤0.25mm are often created through other means because the costs of the preformed spheres are not yet competitive.
Alloy types. Eutectic Sn/Pb solder is the most prevalent alloy used in WLPs today. Other alloys are also available, including high-Pb (95Pb/Sn) alloy, used for power applications, and Pb-free alloy, used to address alpha particle-sensitive or environmentally conscious "green" products.
Routability and special features. The routing of traces on a WLP depends on the packaging manufacturer's design rules. For nonimpedance-matched traces, line and space features are often maximized and 90° angles are eliminated to reduce current crowding. Metal traces will typically flare out at the ball site to minimize stress and current crowding. Other design considerations address features such as fuse links or probe pads. These features may need to be preserved or made available after WLP conversion and need to be pointed out to a WLP manufacturer during initial evaluation.
Backgrinding. Thinner silicon increases thermal cycle reliability and supports lower-profile products. The extent to which a wafer can be thinned depends on wafer diameter and the WLP process. This is because thinning can generate damage in a wafer surface, giving rise to microcracks and causing eventual breakage during subsequent operations. For these reasons, backgrinding is one of the final steps in the wafer fabrication process, and the extent of device thinning may be limited in a WLP process. It is wise to consider wafer-level packaging as an extension of the wafer fabrication process, and to view the applicability of subsequent process steps within this context.
 Figure 6. The Nokia 3285i mobile phone contains two EEPROMs that are provided in a WLP, shown here with backside marking. Photo courtesy of Prismark/IECC |
Backside marking. Backside marking is used for identifying part numbers, lot numbers, orientation marks, and company logos (Fig. 6). Backside marking guidelines depend on tooling and techniques used by WLP service providers. Parameters such as font size, character spacing, pull back areas, etc., must be defined according to the marking technique used. For example, when using a laser marker, optimal legibility depends on the spot size of the laser. In addition, the number of touchdowns, the beginning and end locations, and the depth of the mark must be considered to avoid the creation of stress risers that can cause microcracks within ICs. The backside surface finish also contributes to marking clarity, since nitrides, oxides, or background surfaces will react differently to either the laser energy (reflection or absorption) or to other techniques that may be employed.
Wafer test and burn-in. The ability to perform final test at the wafer level produces significant cost savings over the testing of individual packages. ICs that currently use wafer-level packaging, such as IPDs, EEPROMs, and analog devices, do not require wafer-level burn-in (WLBI). However, WLBI will be required for next-generation high-I/O DRAM. WLBI of DRAM WL-CSPs is on roadmaps that target capability by 2005.
Singulation and packaging. WLP design must address singulation issues, such as material buildup on a saw blade, chip outs, or damage to the structure from the dicing process. For these reasons, redistribution layers are often terminated on either side of the scribe line. Although wafer singulation and subsequent packing in tape-and-reel format is a common way to package and ship these products, some assemblers are requesting that ICs be shipped in wafer form so that components can be picked and placed directly from dicing tape. Wafer maps would ensure the use of known good die and additional costs are saved in the shipping and assembly of components.
Surface mount assembly considerations
The intent behind wafer-level packaging is to be compatible with standard SMT assembly techniques. WLPs with 0.75-0.8mm pitch find rapid acceptance and global assembly capability. 0.5mm-pitch ICs, introduced into volume production in 1999, are gaining rapid acceptance through OEMs. Contract manufacturers are introducing assembly know-how in factories around the world.
As with any new package type, the assembly process must be optimized around the package. This is not only true for WLPs in general, but also for individual WLP technologies, since varying constructions can promote different failure mechanisms and time-to-onset of failure. To illustrate how variations in assembly and package construction can affect board-level reliability, Table 2 lists several parameters and their comparative results for a thin-film redistribution WLP.
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WLP reliability
When evaluating a new wafer-level packaging technology, certain reliability information should be provided by the manufacturer and, if not, requested by the user. For example, the most common failure mechanisms for solder joints should be tested. Solder fatigue, corrosion, and electromigration represent the most common failure mechanisms for solder joints.
Detailed information about test conditions must also be provided. OEM requirements can vary significantly by end application and even similar applications can have a wide range of requirements. For example, a cell phone thermal cycle requirement may be defined as -40°C to 125°C for 500 cycles for one customer and 0-100°C for 800 cycles for another customer. Similarly, a DRAM-SRAM requirement may be -40°C to 100°C for 600-1000 cycles.
Failure criteria must be defined (e.g., 20% increase in resistance over a given period of time).
Statistically significant sample sizes of 22, 45, or 77 units/cell provide increasing degrees of confidence in the results. Smaller sample sizes may show initial feasibility, but cannot be used to project overall reliability performance.
Thermal shock should not be confused with thermal cycle tests. A thermal cycle test should ramp between temperature extremes at a rate not exceeding 10-15°C/min in a single-chamber system. This technique results in time-dependent creep failures of the solder joint, which is the same failure mode seen in the field. This realistic ramp rate will simulate field failure mechanisms even in under-the-hood automotive applications (where it is reported that the thermal ramp does not exceed 5°C/min). Conversely, thermal shock tests were developed for packages with different constructions and failure modes. Temperature-shock transitions at 20-25°C/min create time-independent elastic and plastic deformation within the solder joint, which can result in premature failure. The application of thermal shock testing for WLP, CSP, and ball grid array packages is not recommended.
Both package- and board-level testing must be performed to capture failure mechanisms that do not show up through package-level tests alone.
The proper reporting of temperature cycle data includes Weibull (Fig. 7) or log normal charts. This is very important because the end user needs to understand not just the total number of failures/cell, but the first onset of failure, the cumulative rate at which packages failed, and the slope of the curve. The consistency of the failure mechanism is a most useful piece of data and can help the system integrator predict how much reliability margin a product may have (Table 3).
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Future directions for WLPs
Aside from ongoing efforts to reduce cost, next-generation technologies will continue to focus on increasing reliability to extend the application of WLPs to larger ICs. Other technologies will include the use of alternative alloys, such as Pb-free or high-Pb solder balls. Low-profile applications such as PC cards will drive thinner packaging. IDMs will also seek out WLP technologies that are scalable to 300mm wafers, and that are compatible with emerging Cu and low-k interlayer dielectric technologies. The ability of WLPs to handle more current or higher temperatures will also be required. WLBI techniques will eventually be used to support high-performance memory.
Conclusion
The joint consideration of package and semiconductor design will result in efficiencies in device layout that will improve component performance. Wafer-level packaging leverages a batch-manufacturing process to reduce package costs. All manufacturing steps are simultaneously processed for each device. Because tooling is specific to the wafer, modifications to an IC footprint can be quickly accommodated. Excess inventories of flex interposers, substrates, or other custom materials can be eliminated.
WLP cost scales with an IC and is a function of wafer size, not I/O count. As more devices are accommodated/wafer, packaging costs will decrease proportionally. Wafer-level packaging will continue to be driven by system OEMs as they migrate toward smaller, thinner, and higher-function components.
Acknowledgments
Ultra CSP is a registered trademark and Polymer Collar is a trademark of Flip Chip Technologies; Super CSP is a trademark of Fujitsu Ltd.; Bluetooth is a trademark of The Bluetooth SIG Inc.; and Handspring and Visor Edge are trademarks of Handspring Inc.
References
1. N. Moskowitz, Prismark Partners L.L.C., private conversation.
2. D.H. Kim, "Deformation and Crack Growth Characteristics of SnAgCu vs. 63Sn/Pb Solder Joints on a WLP in Thermal Cycle Testing," ECTC 2001 Proceedings, Orlando, FL, May 2001.
Deborah S. Patterson received her BSEE from the University of California, San Diego. She is director of market development and strategic applications at Kulicke & Soffa, Flip Chip Division, 3701 E. University Dr., Phoenix, AZ 85034; ph 602/431-6020 ext. 212, fax 602/431-6021, e-mail [email protected].