Closing the missing link
05/01/2002
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As following Moore's Law steadily pushes the chipmaking envelope, process latitudes are being squeezed to their limits. It becomes harder and harder to get precise, repeatable results all over a wafer (particularly a 300mm one) and from wafer to wafer. For the most advanced microprocessors, CD variations mean that some chips with higher speeds may be worth hundreds of dollars more than other die on the same wafer. Still, for the most part, the industry continues to keep the design of chips completely separate from the processing side. Fabs communicate their process parameters to designers so they can be embedded in design rules within the electronic design automation (EDA) programs used to structure devices, place the circuitry, and lay out the interconnect patterns. Once the design is done, verification software checks timing and other factors such as power consumption. When the mask patterns are created, there can be another check on whether any design rules have been violated so that the layout can be fine-tuned before first silicon.
That traditional approach worked fine until a few years ago, when timing delays became much more dependent on parasitics in the interconnect (R, C) than gate switching speeds. In a few cases, even after verification, circuits did not work when put onto silicon, and months of redesign ensued. Many circuit patterns are shrunk as process technology advances, and tighter spacing with narrower lines may increase parasitics enough to disrupt timing over the longest traces. After a few bad experiences (including a microprocessor that produced faulty results for some calculations), the industry learned to insert parasitic extraction into the design flow and carefully reverify circuit designs after a shrink. Thus, the separation of design and process engineering was maintained, even though verification now takes up more than half of the design cycle for complex chips.
The problem with the isolationist approach is that designers and process engineers are losing the opportunity to make intelligent tradeoffs. A few simple compromises could make circuits work better and make processing more repeatable and less sensitive to process variation. This potential to better optimize designs was recognized several years ago by DARPA, and a program was devised to create better links between EDA and the technical computer-aided design (TCAD) programs used by process engineers. The idea was that tradeoffs could be explored with simulation, to improve both circuits and processing. Of course, the growing complexity of chipmaking (and circuit design) was also recognized, meaning that even with good simulation software some interchange between designers and process engineers would be necessary to explore alternatives and to choose the best compromises based on the constraints of design and processing methods. Before the program was launched, however, DARPA also realized that power consumption would become a tremendous problem as more devices were squeezed onto chips running at much higher speeds. The available R&D funding thus went to the low power initiative rather than toward creating more interaction between EDA and TCAD.
Now the chickens are coming home to roost. Evidence of the growing need to modify designs to match the capabilities of advanced lithography was everywhere at this year's SPIE Microlithography Symposium (see report, p. 30). Lithographers wondered about all the odd curlicues and irregular patterns that show up on the designs given to them to turn into enhanced reticles. Speakers from all over the industry — TSMC, IBM, Intel — suggested that further constraints will be needed in future circuit designs. One speaker confessed that his group had hesitated to tell the company's designers what was coming because of fears that they would all quit and go to work for the competition. Now that the major players are all agreeing that more limits must be placed on design freedom, he said that it is time to break the news to chip designers. Circuit complexity is evolving into a full-scale crisis, suggested Andrew Kahng, coordinator of the design sections of the ITRS roadmap and a professor at UCal-San Diego. Work to optimize different segments of the roadmap have resulted in a globally sub-optimal process, he charged. ASML proposed a new reticle enhancement technique called chromeless phase lithography (CPL) that would only require a single exposure without pitch restrictions, but more work needs to be done to see whether this will be practical. Many other ideas were discussed, including pre-patterned phase shift mask blanks that are ready to write, but require designers to build circuits along standard grids.
The underlying problem is that the infrastructure to support new exposure tools has not developed fast enough for the generational transitions in chipmaking, so that hard phase shifting, optical proximity correction, and off-axis illumination are all increasingly needed to keep pushing the shrink at low k1 factors. Also, it looks as if this stretching of existing exposure technology will continue for some time, so the industry is either going to come up with a new bag of wavefront engineering tricks or finally get designers and process engineers working together. They will have to collaborate anyway, when CMOS is pushed to the limits and unconventional device structures such as vertical transistors, dual gates, and other variations come along. Why not get started now?
Robert Haavind
Editor in Chief