Technology News
05/01/2002
What's next: Full immersion lithography?
What would happen if EUV lithography were delayed, were too costly, or did not work at all? Would the feature shrink that has advanced Moore's Law end at 70nm? Not if clever optical lithographers have anything to say about it!
One idea to improve resolution without violating the laws of trigonometry or physics is immersion lens lithography. M. Switkes and M. Rothschild of MIT's Lincoln Laboratory, who have been working in this field, reported their latest results on immersion lithography with 193nm and 157nm sources at SPIE in March.
Immersion lenses have been used for a century in microscopy. The idea is to fill the gap between the sample and the objective lens with a medium, usually a liquid, with index of refraction, n, that reduces the effective wavelength [1]. Imaging through the liquid adds a factor of n to the denominator of the usual Rayleigh resolution formula, changing the form familiar to lithographers to CD = k1λ/nNA. Replace the microscope slide with a wafer and make the microscope into a scanner and you have immersion lithography. The DOF is also reduced, of course, but by a factor of 1/n rather than 1/n2.
Since the 193nm wavelength is at the edge of transparency of familiar materials and 157nm is at the edge for all materials, reducing the effective exposure wavelength by a factor of 1/n seems attractive. The "dry" numerical aperture of the projection lenses (currently NA≈0.85) can be increased to nearly unity, but that is likely to produce less improvement than pouring in a suitable transparent liquid medium with an index of 1.4 or so. Switkes and Rothschild identified a family of perfluorinated polyethers (Ausimont Corp.'s Fomblin brand pump oils, for example) suitable for 157nm. At 193nm, the best liquid turned out to be sufficiently pure de-ionized water.
 SEM of a thin layer of LUVR 99071 resist exposed at 157nm via immersion enhanced interference lithography. |
Liquid compatibility with optical surfaces and with resists has been cited as one difficulty, but the Lincoln Labs team has succeeded in patterning 30nm line-space patterns in 157nm resist using interferometric techniques with immersion (see figure). Cleaning the pump oil off a CaF2 prism is less challenging than removing it from a precision scanner lens. Filling the gap between the prism and the wafer can be a problem, but no macroscopic bubbles appeared and the fluid viscosity seemed only to limit scan speed. One observer suggested that liquid argon would be the best immersion fluid — inert, transparent, and easy to remove — except that the 80K temperature would cause lenses to crack and films to lift off wafers due to thermal shock.
Engineers not yet ready to baptize their $8 million scanner lenses in pump oil may have another option: solid immersion lenses (SILs) [2]. In this scheme, proposed by L.P. Ghislain, et al., super-flat wafers are brought really close (<λ/6) to the planar bottom surface of a lens so that the evanescent field (otherwise reflected by the surface) can expose the resist. In the initial experiments, the last lens element was supported on an atomic force microscope cantilever to maintain the necessary closeness to the surface. A 442nm wavelength laser focused into an n = 2.2 SIL patterned 190nm width spaces. Such a one-pixel-at-a-time system may be too slow for wafer patterning, but the laws of optics allow as large a field for an SIL as for a liquid immersion system.
Both systems are likely to suffer from polarization anomalies and short depths of focus, but then conventional "dry" optics will show related effects for NA >0.8. Engineers tend to worry about resist flakes and things such as microbubbles floating around in the liquid film, but their optical effects may be minimal. More serious will be turbulence and thermal gradients, which could systematically deviate and blur the images.
The consequences of a wafer bumping the projection lens (a common occurrence in microscopy) would not be good! The projection lenses themselves need to be redesigned to avoid aberrations due to a uniform liquid film. There is clearly more R&D to be done before the industry jumps into immersion lithography. Fortunately, the early lessons are less expensive than those for other post-ArF systems. But there is much yet to be learned. — M.D.L.
References
1. M. Switkes, M. Rothschild, "Immersion Lithography at 157nm," J. Vac. Sci. Technol., B 19(6), pp. 2353-2356, Nov./Dec. 2001.
2. L.P. Ghislain, et al., "Near Field Photolithography with a Solid Immersion Lens," Appl. Phys. Lett. 74, pp. 501-503, 1999.
An alien technology for assembling ICs
Gravity, one of the most familiar forces of nature, is at the heart of Alien Technology's fluidic self-assembly (FSA) process. FSA is a technique to assemble ultrahigh volumes of crystalline silicon drivers into plastic substrates for displays, RF ID tags, and other portable electronic devices.
The FSA process starts with forming ICs into trapezoidal shapes (called NanoBlocks) with a 54.7° beveled cut using CMP and crystalline-plane-specific chemical etching from a wafer surface. The ICs can range in size from 10 to several hundred microns on a side. When suspended in an aqueous solution over receptor holes in the display, the ICs fall into place, literally. The receptor holes, which have been micro-embossed into the substrate, match the size and shape of the NanoBlock ICs and are placed with an accuracy of ±1μm. The company credits the use of chemical etch instead of a die cutting saw for being able to achieve a ~10μm etching street vs. the typical 100μm sawing street, allowing perhaps 250,000 die from each 200mm wafer.
The law of large numbers governs the actual results of the fall into receptor holes. Those ICs that don't make it are removed from the fluid, cleaned and re-used. A polymer coating on the surface of the aqueous solution prevents damage of the NanoBlocks. Alien, of Morgan Hill, CA, claims a yield rate in excess of 99%. The processing chamber lies between two spindles. A roll of micro-embossed substrate feeds into a chamber slot, so tiny ICs can be washed over the surface.
Tapping the mass consumer markets means keeping costs low — the main reason Alien decided to implement the FSA process on flexible (rather than rigid) displays, for mass production.
"The TAB-like (tape automated bonding) design rules are compatible with our initial product, embedded displays for Smart Cards," explains Anne Chiang, VP of product engineering and displays. "We've chosen to use continuous roll-to-roll manufacturing to meet low cost/high volume objectives."
The production line is planned to be operational in 2003. The company is staking its future on its ability to be able to place between two and four million ICs/hour, or more, within the next year, compared to 10,000/hour with present machines. Company VP of finance and CFO John Hemingway believes the company will be able to assemble tens of millions and even billions of ICs for pennies in 2004. — D.V.
A futuristic AVS Conference
From air gaps to atomic layer deposition (ALD) at room temperature, to CVD vs. SOD and VICs (vertically integrated circuits), the recent AVS Conference on Microelectronics and Interfaces voyaged to the future.
VIC, a 3D-integration technology, is being held out as hope by Infineon Technologies' M. Engelhardt for the manufacture of ICs several generations beyond the limits of optical lithography. The idea is to use interchip vias for electrical connections in what is essentially a wafer stack, with the top wafers being thinned and glued onto planarized bottom wafers. The Infineon technique uses only CMOS-compatible processes and no wafer backside processing. Because the process uses fully processed and electrically measured/tested product wafers, overall yield may be limited by the ability to have perfect bonding of the vertical interconnects.
Another futuristic pursuit that will rely on reliable manufacturing processes is the use of either porous low-k dielectrics, or even air, coupled with Cu to minimize the RC delay of the interconnect structure (paper presented by S.V. Nitta of IBM T.J. Watson Research Center). While David Wang, president and CEO of ACM Research, thinks using air is a good idea, he hasn't seen a viable approach published that can be used in semiconductor devices, taking into account multilayer structure and device reliability. "However, nothing is impossible until we try it," Wang says.
 Figure 1. Roadmap to 45nm technology using CVD low-k dielectrics. |
Trikon Technologies' Andy Noakes, CVD products marketing manager, reports that the company is betting that CVD low-k dielectrics are the right way to go rather than SOD (Fig. 1). "CVD will beat SOD because it is lower cost and presents less risk," states Noakes. "The industry has used CVD for years and logic manufacturers will choose CVD over SOD every time if the results are equal." Noakes does add that SOD is extendible down to k values of about 2.0 and maybe a bit below, so the challenge for CVD is to match these results; International Sematech (ISMT) is addressing the issue.
ISMT project engineer Jeff Lee presented results of its evaluation of Trikon's Orion CVD dielectric material. This showed the feasibility of integrating it in single-level metal Cu damascene test structures. The material met ISMT's specifications for characterization at the one-level build and the organization will continue to test the material over 4-6 months, noting that
the material needs to be optimized for etch, ash, CMP and other processes.
Judging by the number of papers, interest in ALD is growing. While ALD above 200°C has achieved some measure of acceptance as a manufacturable process, doing so at lower temperatures (possibly as low as room temperature) is still being evaluated. The interest in room-temperature ALD is spurred by the growing requirement to minimize thermal budgets (e.g., minimize diffusion of dopants), as well as fulfilling a need to explore applications such as deposition on plastics. Arthur Sherman, president of Sherman & Associates, believes deposition of Cu seed layers could possibly benefit from a low-temperature ALD process as a way to lessen agglomeration effects that occur. He speculates that in the future growing amorphous metals, which could be excellent barrier layers, could be done using room-temperature ALD to prevent film crystallization.
 Figure 2. Initial results of Ta deposition using PEALD; XPS depth profile. |
Sherman, and others (IBM Research, UC Berkeley), have already demonstrated room-temperature deposition of aluminum oxide, titanium and titanium nitride. Recently, ASM/Genitech reported preliminary data on low-temperature tantalum (Fig. 2). "I think the first commercially viable low temperature ALD process will be for high-k gate oxides, because growing a 30μm film uniformly over a 300mm wafer needs an inherently very uniform process," predicts Sherman. — D.V.
No FIBbing — next-generation failure analysis hits bottom line
As semiconductor manufacturers race against the industry roadmap, failure analysts have had to keep up their end of the design cycle/product cycle equation so the bottom-line enablers — yield enhancement and advanced process development — proceed efficiently.
Being able to remove very small amounts of material in a controlled fashion is key to discovering the true nature of a failure. Many in the field have been evaluating and using focused ion beam (FIB) as an adjunct to, or even replacement for, mechanical sectioning techniques.
FIB has been used for years to repair chips or do minor design changes, but, when used properly, it can accomplish cross-sectioning without causing damage or compromising the nature of the defect being investigated. The growing use of low-k dielectrics adds to the failure analyst's burden of preventing the destruction of failure evidence during the course of the investigation, however.
The reduced modulus of elasticity and porosity of the new dielectric films prevents use of the once tried-and-true manual sectioning in which oxide surfaces are polished until they are smooth. Soft materials have a tendency to smear, while the brittle ones have a tendency to fracture during traditional failure analysis preparation.
In light of the new challenges, even FIB is limited in what it can handle. For example, the beam can interact with low-k dielectrics. Gate oxides, which can be ≤2nm in thickness in advanced CMOS technologies with ≤130nm gate lengths, are becoming more and more difficult to probe (Fig. 1).
Sub-0.25μm features cannot be optically imaged using conventional tungsten wire contact probes. Furthermore, when FIB CVD tungsten deposition is used to form probing pads, the result can be the unwanted implantation of gallium into the top surface of porous, low-k dielectric films.
To combat these problems, failure analysts are exploring atomic force microscopy (AFM) to precisely position multiple probe tips within a small footprint and perform electrical measurements on features as small as 0.50nm [1].
"AFM as an electrical characterization tool for contact and noncontact probing has begun to supplant conventional tungsten wire contact probing in CMOS SOI structures involving low-k dielectrics," notes Terry Kane, senior engineer at IBM Microelectronics Division.
"These devices, which use partially depleted device designs that produce floating body effects, are prone to charge build-up. This results in gate oxide damage
upture as well as gallium implantation into the low-k dielectric films," says Kane (Fig. 2).
 Figure 2. Ion beam damage caused by 30kV Ga ions. (Courtesy of Microelectronic Failure Analysis Desk Reference 2001 Supplement, ASM International) |
The transition by IC manufacturers to the far more valuable 300mm wafers is another major driver and companies are vying for an edge in analytical techniques just as much as in their product designs.
"It used to be that design engineers didn't especially like to see failure analysts," says Ed Cole, a distinguished member of the technical staff in the Failure Analysis Department at Sandia National Laboratories. "Now, considerable revenue is being generated by IP from failure analysis techniques and, more and more, the field is being viewed as giving a company a competitive advantage."
Part of the competitive advantage is accelerating the process. In the rush to find short cuts, the emphasis on photographing defects may have to be reduced. "If we can omit defect identification or characterization and still identify the cause of failure, we avoid a sizable amount of work intended to give a picture of a defect in a circuit and provide an analysis of its chemical composition," notes Steve Ferrier, president and CEO at SDG Analytic. "We would like to escape the over-dependence on pictures of defects [e.g., SEM, EDS, TEM] because of the time required to find, photograph, and characterize them."
Cole figures that if a modern IC fab is down because of an unresolved defect that produces a failure, the direct costs can easily exceed $1M/day, depending on the product. "If there is a delay in getting a product to market before your competitor who has better failure analysis tools, then the loss in market share makes the impact critical to the profitability and survivability of the manufacturer," Cole notes. — D.V.
Reference
1. "Electrical Characterization of Circuits with low-k Dielectric Films and Copper Interconnects," T. Kane, P. McGinnis, B. Engel, IBM Advanced Semiconductor Technology Center, ISTFA 2001 Proceedings.