Progress in RETs, NGLs, and more reported at Microlith Symposium
05/01/2002
These are gut-wrenching times for lithographers. They are pushing the limits of light deep into the sub-wavelength regime using resolution enhancement techniques (RETs). They're also struggling to devise future next-generation litho (NGL) systems based on shorter wavelengths, perhaps x-rays or electron beams. The status of the various contenders, plus the infrastructure to make them commercially viable, were probed at the recent SPIE Microlithography Symposium.
This year's meeting, in sharp contrast to a year ago, was marked by a mood of distinct consternation. A year ago, in a keynote speech, Dennis Buss of Texas Instruments observed that lithographers had made so much more progress than the rest of the industry that their R&D was off the critical path until other areas (like gate oxide) caught up.
But over the past year, excessive intrinsic birefringence in CaF2 — the key material for 157nm litho tools — was discovered, delaying that program, and no 157nm pellicle material appeared from the polymer labs. The "moon shot" character of the EUV (extreme ultraviolet) enterprise became clearer and the 2001 ITRS roadmap appeared with steeper demands on gate uniformity, line edge roughness, and other parameters.
Many papers detailed the difficulties of implementing advanced RETs needed for 100nm devices and beyond as the industry attempts to push from one generation to the next over two year cycles. This pace was called for by Robert Helms, president and CEO of International Sematech, in his plenary address.
"The industry does not really have the resources to meet the challenges of such a schedule," warned one Sematech member company executive. "We could kid ourselves into collapse, like the telecom industry."
While there is steady progress across the lithography spectrum, from sub-wavelength reticle enhancement on 248nm steppers to next generation options, it appears that optical stepper/scanners will remain on the job down to 70nm and perhaps well beyond. But it won't be easy.
The coming troubles were apparent in numerous reports and panel discussions. Lithographers are struggling to find ways to print features below 100nm without limiting circuit design flexibility, but it may not be possible. One confessed that at his company they had been afraid to tell designers about new restrictions, because of the fear they would "quit and go to Intel." But speakers from Intel, TSMC, IBM and other major players all suggested during the Symposium that new types of design restrictions, and even more regular, perhaps grid-like, circuit patterns may be necessary to meet future tight-tolerance CD requirements.
A new focus on design
New at the Symposium this year was a meeting on Design and Process Integration, chaired by Alex Starikov of Intel and Robert Pack of Cadence. The meeting offered an opportunity for EDA-tool developers, chip designers, and fabricators to exchange ideas. A survey of the audience at a key panel session indicated, however, that no chip designers were there.
Future challenges were probed by Burn Lin, senior director of micropatterning, TSMC, in one of the plenary talks. In particular, Lin saw a disconnect between the business-oriented demands for narrow, fast gates with minuscule variation (i.e. 45nm ±4.5nm (3σ) at the 90nm node) and today's most heroic results of only 8.5nm (3σ). According to Lin, a foundry today is faced with too many pitches and too many environments to be able to optimize everything to that level, especially in the face of reticle CD error, wafer flatness and other realities.
Contemplated solutions with shorter wavelength exposure may introduce as many difficulties as they solve, especially if the introduction is delayed. Lin warned that even the swing curve would be enough to close the process window for EUV contacts at the 40nm node. Lithography-friendly design and multiple exposure schemes may allow the shrink to continue, Lin suggested, but at the price of more restrictive ground-rules and higher costs.
In his keynote address, "Crossing the Divide Between Lithography and Chip Design," Bill Arnold of ASML highlighted the trade-off between design flexibility and yield at low k1. While lithography system developers work very hard to insure proper patterning for lines and spaces at the minimum rated pitch, various unfortunate things can and do occur at larger dimensions and for other structures (particularly contacts). The exact failure modes depend, however, on the particular resolution enhancement technique (RET) embraced by the lithographer. Severe design rule restrictions may allow optical lithography to survive until the 45nm node, but better communications between chip designers and lithographer will be essential, according to Arnold.
 GRATEFUL examples. a) 70nm fine features in x and y; b) 65nm gate features through pitch. (Source: Fritze et al., SPIE Proc., Vol. 4346, 2001.) |
Lars Liebmann of IBM related the lessons from Big Blue's experience in trying to implement strong RET at the 180nm node. These lessons are especially significant as the early learning for the "70nm node" (with 160nm pitch, gate CDs of 45-65nm and 3σ<3.7nm), which will have to be done using 193nm exposure tools with RET.
According to Liebmann, "The design-rule, -tool and -methodology modifications required to implement strong RET can be supported, but they require a high level of commitment and a distinct lack of alternatives." He predicted that re-engineering the design process to be strong-RET-compliant will take two full years, but will be a key factor for success at 70nm.
Brian Tyrell of MIT's Lincoln Labs recounted the advantages of a restricted design scheme that fabricates devices with dense-only phase shift grating masks, thus avoiding "forbidden pitches." While each level would have to be patterned using multiple masks and resist exposures, this system has already printed 70nm line space patterns and circuit gates using 248nm illumination (see figure).
Tyrell found that a 125nm-node, 2-input NAND gate could be laid out with 4.875μm2 area, below the 5μm2 roadmap value, in spite of the design constraints. A full adder circuit with all gates parallel also showed no density penalty. With proper trim mask design, overlay errors of ±50nm are reported tolerable. Marc Levenson, a consultant, observed that the required grating masks could be mass-produced inexpensively by wafer fab techniques if the phase gratings were standardized.
Crisis in circuit design complexity?
Prof. Andrew Kahng of UCal, San Diego, and coordinator of the design sections of the ITRS roadmap, described an escalation of the complexity of circuit design into a full-scale crisis. According to Kahng, the attempts to optimize individual segments of the semiconductor roadmap have resulted in a globally sub-optimal process in which quality trades off with flexibility.
Design first appeared as a Roadmap section in 2001, but it is now being asked to cope with too many problems with too few resources, reported Kahng. Embedded software is the main design expense. Even though embedded microprocessors are 10,000 times less capable than custom hardware, they are routinely included as time saving work-arounds to meet critical schedules. The increasing time and cost required for custom design make new chips less worthwhile to make. According to Kahng, the design community is suffering from a drought of independent R&D funding as well as pervasive schedule acceleration. Testing new ideas is just not possible in such an environment. Solving the red-brick problems on the roadmap will require the technology areas to share responsibility as well as funding with chip designers.
The Design conference also included a panel discussion on the topic: "Do We Need A Revolution in Design and Process Integration to Enable Sub-100nm Technology Nodes?" moderated by Pack of Cadence. low-k1 imaging seems to be driving mask complexity and costs unacceptably higher, while making process windows smaller in spite of the best efforts of the resist, EDA, and exposure tool suppliers, who have produced too many options.
The panel consensus was that a train-wreck was coming, but it might be averted by rapidly adopting a RET-enabling design-to-silicon paradigm, so long as it was transparent to the chip designers. It might even be that the new restrictions would end up reducing the need for guard-bands on design rules, thereby increasing functionality.
Burn Lin of TSMC speculated that litho friendly designing might actually be simple to explain: avoid forbidden pitches, critical two-dimensional patterns, and non-Manhattan geometries; line up gates; and reduce the range of pitches and the number of critical feature types on each layer. That would be a tall order, and legacy designs might be a problem, of course.
"A revolution is not a rose garden. It is a struggle to the death between the past and the future," said Lars Liebmann of IBM, quoting Fidel Castro. Extrapolating the slow progress over the last five years, Liebmann predicted that RET-enabled design would not be ready for 70nm. This would leave the industry with no ability to shrink chip dimensions at acceptable yield. "Tuning the design to the litho technology requires knowing what litho technology is going to be used, and that is never decided until two years after the design begins. It would take time travel to make that work," Liebmann quipped.
Warren Grobman of Motorola summed up the discussion by noting that no one present thought that the industry could muddle through without major changes until EUV technology comes along to make high-k1 lithography viable again. Everyone agreed that something has to be done, most likely involving an acceptance of design constraints implied by simulation of future processes. However, no active chip designers attended the panel discussion. Also, no one had a good suggestion for how to reach out to them and enable the restrictions required by the perceived limits dictated by the laws of physics and chemistry.
See the next issue for Part 2 of the coverage of the SPIE Microlithography Symposium.