Device scaling drives pattern effect solutions
05/01/2002
by P.J. Timans, Z. Nényei, Mattson Technology, Fremont, CA
R. Berger, Infineon Technologies, Regensburg, Germany
Overview
As device scaling continues to tighten process control requirements in advanced semiconductor manufacturing, a new challenge is emerging in the field of thermal processing. Pattern effects — arising from the effect of patterned thin film coatings on radiation heat transfer — can lead to process nonuniformity and defect generation. In essence, wafer temperature uniformity can be limited by the influence of device patterns on heat transfer. This paper describes the physics behind the effect and illustrates the impact on process uniformity in rapid thermal oxidation and annealing, as well as the effect on lithographic overlay control. Potential solutions are presented.
The pattern effect issue will become even more important as die sizes increase with innovations such as embedded DRAM and system-on-a-chip (SOC) technology. The advent of silicon-on-insulator (SOI) substrates is also significant because these wafers inherently contain silicon-on-oxide structures that can have a major influence on thermal radiative properties and heat transfer.
Rapid thermal processing (RTP) is the leading approach for thermal processing of semiconductor wafers, especially for advanced devices and for 300mm wafer processing [1, 2]. Key applications include oxidation, ultrashallow junction (USJ) formation, and silicide reactions. As device technology advances, the need for improved process control has stimulated many innovations in RTP equipment technology, especially in the area of temperature measurement and control. One critical requirement is for thermal uniformity across the wafer to ensure process uniformity and to minimize thermal stresses that could introduce defects. State-of-the-art RTP systems have been shown to demonstrate temperature control better than 2°C 3σ across process monitor wafers.
Origins of the pattern effect
The fact that patterns of thin-film coatings that cover the die on a wafer can have a major impact on the temperature uniformity during thermal processing was already recognized in the early days of RTP. Several experimental and theoretical studies have addressed the topic [3-7]. The origin of this phenomenon arises from the nonequilibrium conditions in an RTP system, where the wafer is not at the same temperature as its surroundings. In a typical RTP system, the energy source is a bank of tungsten-halogen lamps, typically at a temperature greater than 2000°C, while the process chamber walls are relatively cool, less than 400°C. The RTP process temperatures are typically between 500 and 1100°C. Heat transfer is dominated by thermal radiation from the lamps to the wafer and from the wafer to the chamber walls.
The large temperature differences enable the fast heating and cooling and the remarkable flexibility of process control that are characteristic of RTP processing. A fundamental problem arises from the nonequilibrium conditions, however, because the optical properties of the wafer affect both the absorption of energy from the lamps and the emission of energy to the chamber. As a result, the wafer temperature is affected by coatings on the wafer surfaces [2].
It is thus essential to have a closed-loop approach for wafer temperature control, where a pyrometer measures the wafer temperature and provides feedback to the control system regulating the lamp powers. The challenge in this approach is to perform a high-speed, high-accuracy pyrometric measurement on a wafer of unknown spectral emissivity in surroundings where a large amount of stray radiation is often emitted from the heating lamps. That problem has been addressed by innovations such as Luxtron Corp.'s ripple pyrometry approach, which is now in use on many RTP tools [8]. These techniques, combined with sophisticated power control, have led to the excellent temperature control that can be shown on monitor wafers, even when there are thin-film coatings on the wafer backside.
 Figure 1. Total normal absorptivity of bilayer structures with a silicon film over oxide. (Reprinted from Ref. 2, p. 201. Courtesy of Marcel Dekker Inc.) |
Figure 1 shows results from a theoretical calculation of the effect of a thin-film coating on the total normal absorptivity of a silicon surface [2]. This property describes how much lamp radiation is absorbed by the wafer. This very simple coating, which consists of a layer of polysilicon on top of a film of silicon dioxide, has a very strong effect on the lamp power coupling, causing it to vary from 0.4 to 0.8 [dimensionless] depending on the thicknesses of the two constituent films. There is a similar impact on the integrated thermal emissivity, which determines how much heat the wafer radiates to the chamber walls.
Coatings can have a profound impact on the thermal cycle of a wafer in an RTP system. For example, if the coating is patterned so that it is only present in parts of the wafer, then the coated and uncoated regions of the wafer may experience different temperature-time cycles during processing. The resulting temperature nonuniformity is the "pattern effect," which can have a major impact on process uniformity and on defect generation. It is important to realize that a closed-loop temperature control system can only correct for the effects of coatings in the region close to where it is measuring the wafer temperature.
Silicon is a good conductor of heat, and lateral heat conduction within the wafer plane minimizes the temperature gradients, thereby reducing the temperature nonuniformity induced by the pattern. As a result, this nonuniformity is strongly affected by the pattern's length-scale. The effect of length-scale can be illustrated by a simple one-dimensional heat-flow calculation based on the equation describing thermal conduction in a sheet of material with thickness D and thermal conductivity K:
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In this equation, x is the position, h(x) is the power coupling efficiency, P(x) is the incident power density distribution, σ is the Stefan-Boltzmann constant, T(x) is the temperature and Heff(x) describes the emissivity for thermal radiation. For small temperature deviations, the T(x)4 term can be approximated with a polynomial expansion, allowing Eqn. 1 to be linearized in the form:
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where ΔT(x) = T(x)-T0 describes the temperature nonuniformity around the average temperature, T0.
Figure 2 shows predictions based on Eqn. 2 for the temperature nonuniformity expected when a wafer that has a region that is coated with a stripe of material with a different power coupling efficiency is heated to 1000°C. The figure illustrates the impact of various stripe widths in the case where the stripe has the effect of increasing lamp power absorption by 10% compared to the value of 0.7 for the surrounding wafer. The calculations were performed for an Heff value of 1.4, corresponding to the radiation from two surfaces of a wafer, each with an emissivity of 0.7. The thickness of the wafer was 775μm, as is typical for a 300mm wafer. The temperature nonuniformity becomes small as the stripe width decreases below ~1mm, although it is interesting that even a 0.5mm stripe leads to a nonuniformity of ~1°C. For stripes >50mm wide, the temperature deviation tends toward an asymptotic value of ~38°C, which corresponds to the limit where thermal conduction has no impact. Since this calculation only applies when there is a rather small change in power coupling — far less than the range shown in Fig. 1 — one can conclude that pattern effects can easily be the main cause of process nonuniformity in RTP.
The pattern effect can also have an impact on temperature transients, and here the behavior becomes complex because the time-scale for lateral heat flow becomes relevant. In RTP, the transient thermal nonuniformity during the ramp and the cooling stages of a recipe can play an important part in determining the nonuniformity observed in process results [9].
Observations of pattern effects and solutions
The pattern effect is well illustrated by a very simple experiment [10]. A double-sided polished silicon wafer was patterned on one side with a checkerboard pattern of a coating known to be highly reflective to lamp radiation. The coating was a two-layer structure with 110nm of polysilicon on top of 200nm of silicon dioxide, and the squares had sides that were 10mm long. The wafer was processed through a rapid thermal oxidation of 30 sec at 1150°C, and the oxide thickness distribution was mapped using high-resolution ellipsometry. The thickness measurements were performed on the unpatterned side of the wafer. The oxide thickness distribution over a square of 40 x 40mm is presented in Fig. 3a.
The map was scanned with 30 x 30 points, i.e., a resolution of 1.33mm. In this case, there is a very large process nonuniformity associated with the pattern, with an oxide thickness variation of ~19Å that corresponds to a steady-state temperature deviation of ~25°C. In an era in which process control targets can be specified as uniformity with 3σ less than 2°C, this is a sobering lesson in the significance of the pattern effect.
Pattern effects have also been observed in sheet resistance measurements performed after rapid thermal annealing of ion-implanted wafers. In this experiment, the backsides of chessboard-patterned wafers were implanted with 1 x 1015 cm-2 As at an energy of 1 keV. The squares of the chessboard contained either plain silicon, or structures with patterning that might be expected for logic-device technology [10]. Implant annealing was performed at 1100°C for 1 sec in an ambient of 10% O2 in N2. The ramp-up rate was 50K/sec and the ramp-down rate was 30K/sec. The target sheet resistance was ~200 ohm/sq. The temperature sensitivity of the sheet resistance had previously been established as 1.1 ohm/sq. Some wafers were annealed in a standard, double-sided heating system, while others were processed in an experimental single-sided heating system that only illuminated the patterned side of the wafer [14]. Sheet resistance measurements were taken at 1mm intervals along a line crossing the chessboard pattern (Fig. 4).
 Figure 4. Effects of heating configuration on pattern effects during rapid thermal annealing. |
Solid circles represent the data from the experiment performed in the experimental reactor. In this case, the sheet resistance variation was 42 ohm/sq., which corresponds to a temperature range of about ΔT = 38°C. In contrast, the results from the double-sided heating approach showed a variation of 22 ohm/sq., which corresponds to a range of about 20°C. The single-sided heating approach requires significantly higher lamp-power density irradiating the patterned surface during the ramp than is needed with double-sided illumination. Consequently, patterns induce larger lateral temperature gradients in the wafer [9].
The impact of patterns is not limited to process uniformity, and it is possible that the most difficult issues may arise from the need to eliminate defects. Pattern overlay control is likely to pose one of the most severe challenges for fabrication of advanced devices. Thermal nonuniformities can introduce dislocations and micro-slip leading to the phenomenon known as "continental drift," where lithography registration marks move. This pattern distortion may limit the ability to perform the necessary overlay, an issue that has been studied [11]. Theoretical — as well as experimental — studies have shown that pattern effects can lead to significant stress distributions in wafers [7].
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Methods for addressing the pattern effect
The pattern effect undoubtedly poses one of the most significant problems for thermal processing of advanced devices, and innovative solutions will be required to address it. In particular, it is essential to optimize the heating configuration. One approach involves the use of hot shielding technology. An opaque plate is positioned between the patterned surface of the wafer and the lamps above the wafer. By driving this plate through the same temperature-time cycle as the wafer, it is possible to maintain a condition of thermal equilibrium between the top plate and the wafer.
Under these conditions, it has been shown that the optical properties of the patterned surface have no impact on the thermal cycle [2]. Figure 3b shows results from the same RTO process used to illustrate the pattern effect in Fig. 3a. In this case, the oxide thickness variation was ~2Å, showing that the hot-shielding approach reduced the process temperature range from 25°C to <3°C. Likewise, in Fig. 4, the combination of double-sided illumination with hot shielding leads to a significant improvement in temperature uniformity, reducing the temperature range to ~4°C.
The impact of pattern effects on lithographic overlay control and solutions for these problems were recently reported for the case of a BPSG (borophosphosilicate glass) reflow process [12]. Optical micrographs showed an increase in slip-line density after RTP processing, especially on wafer areas where chips were close to the wafer edge and the unpatterned periphery of the wafer and near the notch. Comparison of the overlay residual was performed on split lots processed with two double-sided heating configurations.
In one case, heating was performed with a quartz liner plate above the wafer. This plate, which transmits the light from the lamps, is often used in BPSG processes because it simplifies chamber maintenance by collecting any products that outgas from the BPSG film. The second configuration had the hot shield above the wafer. The hot shielding approach significantly improved the overlay control (see table on page 70). Furthermore, Fig. 5 shows the impact of the hot shielding approach on the spread of sheet resistance measurements obtained from process control monitor structures that are used in these experiments and in production. The hot shielding approach leads to a tighter distribution of values.
 Figure 5. Impact of hot shielding on the spread of sheet resistance measurements obtained from process control monitor structures. |
Other RTP approaches may also evolve to combat the pattern effect. For example, systems based on hot-wall concepts may benefit from reduced pattern effects because the process temperature is close to the chamber wall temperature. Systems that attempt to heat the wafer predominantly by thermal conduction through a very thin layer of process gas also offer an approach for reducing pattern effects, although here the need for tight control of the dimensions of a small gap between the wafer and the heat source poses formidable technical challenges [2].
Conclusion
Pattern effects present the last frontier for temperature control in RTP and in advanced CVD technologies [13]. As device dimensions shrink and die sizes rise, the issue of handling these effects becomes increasingly important. In advanced circuits, new issues are also expected to arise from requirements on intra-die uniformity, since processing variations within a die could degrade circuit performance. Defect generation from local thermal stresses and the associated overlay issues will also drive the need for resolution of this issue. RTP processing techniques will need to address these challenges through further advances in temperature management. Hot shielding is an approach that results in a significant improvement in temperature uniformity and a tighter distribution of process results.
Acknowledgments
The authors would like to thank W. Dietl, S. Buschbaum, J. Niess, K. Meyer, and S.P. Tay of Mattson Technology; S. Miethaner and H. Gruber of Infineon Technologies; and R. Wahlich of Wacker Siltronic AG, for help with the experiments described in this paper.
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Paul Timans received his PhD from Cambridge University. He is director of technology for the RTP product business unit of Mattson Technology and has 18 years of experience with semiconductor process and equipment technology. Mattson Technology, 2800 Bayview Drive, Fremont, CA 94538; ph 510/492-5992, [email protected].
Zsolt Nényei received his PhD from Technical University Budapest. He is a Mattson fellow with more than 30 years of experience in semiconductor process technology. He has authored or co-authored 15 patents and more than 50 technical papers.
Rudolf Berger received his degree in material sciences and his PhD in electronic devices from the University of Erlangen-Nürenberg. He is a process engineer for hot processes at Infineon Technologies.