High bandwidth interconnects via a novel chip-stack package
04/01/2002
by Eric Beyne, IMEC, Leuven, Belgium
Overview
Continued evolution of VLSI technology demands an increasing number of interconnects between ICs and other system elements. For short interconnects, electrical signal lines still maintain the highest capacity and speed. To keep up with increasing speed and density requirements, thin film multichip modules will increasingly have to be used. Proposed here is a 3-D chip-stacking technology that addresses both future requirements and the limitations of previously published methods.
The rate of change in packaging significantly lags IC manufacturing, so we are seeing a growing gap between VLSI chip and packaging-and-interconnect technologies. About 10 years ago, thin-film multichip modules (MCMs) were proposed as a solution for the increasing wiring demands of ICs. Due to economic constraints and the adaptability of competing PC-board and ceramic technologies, this did not happen. Competing technologies were able to push their capabilities to new limits and solve most interconnect problems. Now, with the coming generations of ICs, we face these issues again.
Most industry roadmaps show IC complexity growing faster than integration capabilities. An almost inevitable result of this is an increase in chip area and pin count (i.e., Rent's rule). Within a few years, this will result in ICs with 40μm peripheral wire bond pads. Even using flip-chip interconnects distributed across a chip's surface, a 100-pin-count die will have a full area array flip-chip pitch of ~100μm and a 900-pin-count die, ~300μm. The limit for reliable assembly of packages with laminate and ceramic interconnect technologies is ~100μm minimum pitches.
Multilayer thin-film technology
We see a solution to IC wiring demands in thin-film multilayer technology based on aluminum and copper interconnect lines combined with photo-sensitive dielectric layers. Linewidths and spacing of 10μm can be achieved cost-effectively using conventional mask processing on 200mm wafers or step-and-repeat lithography for large-area substrates.
Some experts argue that systems will be integrated fully on a single die (i.e., system-on-a-chip or SOC), thus requiring only limited interconnects. We believe, however, that technological limitations, system diversity, and economic realities point to a system-in-a-package (SIP) approach: As integration of functions becomes more successful, electronic subsystems will become smaller and more attractive to build as a single module. The interconnecting substrate will combine the roles of high-density IC and module interconnects. For the latter, the module will "translate" very high density die-level interconnects to the coarser pitch of PC boards, similar to the "interposer" substrate used in a BGA package.
An ideal thin-film technology should therefore be realized on a laminate substrate base, similar to MCM-SL/D technology [2]. This approach uses a laminate interconnect substrate fabricated with conventional build-up PC board techniques. To be appropriate for further thin-film processing, materials are selected to be thermally compatible (200-250°C) and the surface has to be flat within a few microns (e.g., by applying a sacrificial resin layer to the board and subsequently backgrinding it to re-expose copper tracks and filled gaps between tracks).
Thin-film digital interconnects
To realize high-speed connections, thin-film interconnect lines must be carefully designed. Generally they are designed as ~50Ω transmission lines, mainly using strip and microstrip lines. A microstrip line consists of a metal conductor of a given width (Wc) and at a given distance (Hd) to an AC ground reference plane. Wc/Hd and the effective dielectric constant determine this line's characteristic impedance. Wc/Hd is ~2 for thin-film low-k dielectrics (e.g., Cyclotene is k = 2.7). For ceramic technologies, it is closer to 1. Therefore, conductor linewidths of 10-20μm need a dielectric thickness of only 5-10μm. Such dimensions are compatible with thin-film fabrication technologies, but are out of reach for laminate or ceramic technologies. If the latter are used, they would require more interconnect layers to achieve the desired routing density.
Another important element in high-speed interconnects is cross-talk between parallel lines. The conductor spacing (Sc) to dielectric thickness (Hd) ratio mainly determines cross-talk between microstrip lines. The relation is nearly exponential and a Sc/Hd ratio of 3 generally results in acceptably low cross-talk levels, which also favors thin-film interconnects rather than laminate or ceramic technologies.
The increased interconnect density of thin-film technologies comes at a price, however — increased line resistance. At low frequencies, a lossy line will behave as a dispersive RC-line, resulting in degradation of signal rise time. When using electroplated copper lines, the resistance of thin-film lines can be somewhat reduced. However, at higher frequencies, skin effect will increase line losses and cause additional degradation of signal rise time. Losses in a line degrade signal shape, but reduce ringing and cross-talk problems.
Interconnection lengths on a module should be kept short to avoid the need for line terminations, which would increase power dissipation significantly. For typical interconnects between an ~50Ω output circuit and a high-impedance input circuit, long lines would result in multiple reflections and ringing. The critical length of a line corresponds to the length propagated by the signal in half the signal rise-time. For a typical low-k thin-film technology, critical length is ~2cm for a 200 psec signal rise time.
For longer lines, matched load termination should be used, but dispersion caused by resistance and skin effect will degrade signals and limit interconnection speed. Matched loads will also increase the power dissipation of a circuit. One possibility for keeping interconnect lines shorter than the critical line length is to stack ICs in the third dimension.
3-D interconnect technologies
Most of the four basic types of 3-D interconnect technologies proposed so far are characterized by low interconnectivity in 3-D [3]:
- Stacked-die wire bonded in a single package gives the lowest interconnectivity.
- A stack of packaged die (e.g., the ceramic 3-D package technology developed by Fhg-IZM in Berlin [3]), even stacked area array packages, only achieves 1 to 4 connections/mm2.
- Packages with several interconnect layers that connect one or more embedded die along the layer's edges (e.g., 3-D-Cube technology from 3-D-Plus in France) are inherently limited in third dimension interconnections — currently only 2 lines/mm on the edge.
- Interconnects formed through wafer thinning and bonding (e.g., technology developed by Fhg-IZM, Munich [4]), where interconnects between stacked active layers are via tungsten plugs, require specifically designed silicon wafers, wafer bonding technology, and wafer thinning down to the die's active layer.
As a viable alternative to these approaches, we propose achieving 3-D thin-film interconnection with ultrathin chip stacking (UTCS [1]); we propose this method for interconnecting high-pin-count, standard ICs. Briefly described, the method thins ICs to 10-15μm and embeds them in a multilayer thin-film build-up (Fig. 1). Up to three layers of interconnected ICs can be stacked on top of each other. In our work, we have developed a novel method to thin and transfer standard sub-μm CMOS die to a UTCS substrate.
 Figure 1. UTCS cross-section showing embedded 10-15μm thin die interconnected using thin film copper lines and BCB photo-sensitive dielectrics. |
As the bulleted technologies indicate, traditional 3-D interconnect schemes connect different layers at the edges of stacked die, greatly limiting interconnect density. When interconnecting high pin-count devices in the third dimension, a fan-out to a larger perimeter is required, resulting in significantly longer interconnect lines. With the UTCS structure, via connections in the third dimension can be realized in the area around the die using pad sizes ≤50μm, thus providing a very high interconnect density.
Interconnect scheme
UTCS provides main interconnect routing channels that are 50Ω strip lines with a 50μm routing pitch. Very short (e.g., a minimum of ~500μm to ~2x the longest dimension of the die) interconnects are realized in the third dimension (Fig. 2).
 Figure 2. a) Top view and b) side view of UTCS wiring structure and routing between chip contacts and the interconnect lines. |
Our UTCS die stacks are achieved using a novel chip thinning and die transfer technique. This technique involves thinning a die to ~50μm using mechanical back-grinding and polishing while the die are still in wafer form (wafer #1). This step requires a stress-compensated chip build-up and passivation layer. To date, our work has produced only a single interconnect level (Fig. 3); work continues on the three-layer stack.
 Figure 3. The UTCS process flow and resulting structure. |
A ~6μm wax layer is spin-coated onto a silicon carrier wafer (wafer #2). Once singulated from wafer #1, each 50μm thin die is bonded upside-down to the carrier wafer using a thermo-compression flip chip bonder. Then, the mounted die on the carrier wafer are thinned to 10-15μm using an O2-SF6 plasma (i.e., process technology from Tru-Si) that etches at ±3μm/min. The carrier wafer is then diced.
We used a benzo-cyclobutene (BCB) spin-on layer (e.g., Cyclotene) for thin-film build up and die-attach glue. First, we spin a 2-3μm layer of BCB onto an interconnect or host substrate wafer (wafer #3). The previously diced thinned ICs each attached to a carrier die via wax are mounted onto the uncured BCB layer using a thermo-compression flip-chip bonding tool with high position accuracy.
After mounting all die, the BCB layer is cured. The previously used wax layer is selected based on its compatibility with the BCB curing process step; it should hold during curing and release afterwards. The removal of the carrier die is then obtained by heating the wafer, melting the wax and "sliding" the carrier chips from the wafer. Subsequently, the interconnect wafer is cleaned to remove wax residues. This whole process achieves circuit-up die attachment to the interconnect wafer, to within ±10μm.
To electrically connect the transferred thinned die to the UTCS interconnect scheme, we deposit a photo-BCB layer to the same thickness as the transferred thin die (i.e., 10-15μm). This "cavity" layer is removed from on top of the die and within a <50μm perimeter, thus forming a ring around the die. A 5μm-thick BCB layer is deposited to fill and planarize the space within the ring and electrical contacts are opened through this layer to contact the chip bond pads. A metal layer interconnects the chip to the UTCS wiring structure (we used copper, but aluminum could be used), which is fabricated at the same time as the cavity and planarization layers (see next paragraph). Finally, a 5μm-thick BCB layer is deposited, resulting in a rather planar surface onto which the process is replicated for the second and third chips. Chemical mechanical planarization can be used on this layer if necessary.
To realize high-density connections between the metal layer below the die and the metal layer on top of the die, we use a special high-aspect-ratio via structure. Before applying the BCB dielectric layers, a metal stud with a thickness equal to the cavity layer, is plated on the bottom metal layers. This method results in high-yield via connections with diameters as small as 15μm in a 20μm-thick BCB layer. For standard photo-BCB via connections, the aspect ratio is <1:4. Using such high-aspect-ratio vias, a via density well above 100 vias/mm2 is achieved.
UTCS performance
We performed a first order estimation of the interconnect efficiency of UTCS compared to a classic 2-D thin-film multichip module (MCM-D) scheme (Fig. 4). We defined packaging efficiency as the ratio of chip area to module area. We used a simplified wiring model based on Seraphim's model [5]. Our basic assumptions were a 50μm conductor track pitch and a 100μm via pitch, and two-thirds of the chip I/Os were interconnected to other chips in the module.
The data in Fig. 4 show a significant improvement in packaging efficiency for the 3-D stack. The lower density of the die with a small I/O pad pitch (Pb) reflects the size reduction of the IC and does not imply a larger module area. To further improve the density of modules with such die pad pitch, a reduction in track pitch is necessary. A reduction to 25μm is feasible with the current technology (i.e., the realization of copper interconnect tracks using electroplating in a resist mold that allows minimum feature sizes down to 5μm using standard mask exposure tools). Clearly, 3-D UTCS technology reaches its highest density for relatively large die, as the overhead introduced by the routing channels becomes less important in those cases.
A 3-D UTCS die stack has been designed by Alcatel-Space in Toulouse, France. This module interconnects three complex FFT ASIC die, each measuring 15 x 15mm with ~600 I/Os at a 100μm pitch. The overall module size is 25 x 25mm, resulting in a packaging efficiency of 109%, slightly better than the estimate from Fig. 4.
Because we are using thin die and thin interlayer dielectrics, the total thickness of the three-die stack is only 60-80μm. This is important for mechanical [7] and thermo-mechanical [8] performance. Using thin layers between die layers, this 3-D stacking technique allows for a much lower internal thermal resistance than other techniques. By stacking three die on top of each other, though, power density increases inevitably by a factor of three.
We applied the UTCS process to a submicron CMOS test die fabricated with IMEC's 0.35μm technology. These 20 x 20mm die were measured before and after thinning to 50μm, and again after thinning to 15μm and transfer to a host substrate. There were no significant variations in either NMOS or PMOS transistor parameters.
Conclusion
We are proposing a novel 3-D interconnection technique that provides much higher wiring capability than other reported 3-D techniques. This method is particularly interesting for high I/O count die with small pad pitches that require a high degree of interconnectivity. The method also allows for parallel processing of a large number of die stacked on a single wafer. To support this approach, we have developed new techniques for thinning the die, transferring the die to a host substrate, and embedding it in a thin-film multilayer structure.
Acknowledgments
This work was partially supported by the European Commission DGIII, under Esprit contract No. 24910 UTCS. The author acknowledges the contributions of project partners: Alcatel Space, Toulouse, France (in particular Olivier Vendier), LAAS, Toulouse, and the University of Barcelona (ESP); the IMEC-HdIP group, especially Rita Van Hoof for processing and Tomas Webers for module and test structure design; and Nicolas Lietaer for help with CMOS test structure measurements. Cyclotene is a trademark of Dow Chemical Corp.
References
1. European patent rf. UTCS EP99201061
2. E. Beyne, et al., Proc. 33th IMAPS 2000, 20-22 Sept. 2000, pp. 229-234.
3. H. Goldstein, IEEE Spectrum, pp. 46-51, Aug. 2001.
4. H. Reichl, V. Grosser, 14th IEEE MEMS Conf., Interlaken, Jan. 2001.
5. P. Ram, et al., Proc. IITC, Burlingame, June 2001.
6. E. Beyne, Proc. EuPaC 96, Essen, Germany, pp. 83-87.
7. S. Leseduarte, et al., IEEE-CPMT, 23, 4, pp. 673-679, Dec. 2000.
8. S. Pinel, et al., EuroSim 2001, Paris, France.
Eric Beyne received his PHd from the Katolieke Universiteit Leuven. He is group leader for high-density interconnection and packaging at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; [email protected].