Japan explores the minifab manufacturing model
04/01/2002
by Mitsuyuki Yamaguchi, Tokyo Electron Ltd., Akasaka, Minato-ku, Tokyo, Japan
Besides adjusting to a severe economic downturn, the semiconductor industry has had to accommodate an increase in the pace of change in markets. Device manufacturers and tool suppliers alike have felt the impact and, to minimize the effects, have found it necessary to investigate a new manufacturing investment model.
The minifab concept is one candidate, particularly applicable to SOC (system-on-a-chip) manufacturing [1]. To speed its development, several national projects were implemented in Japan in 2001.
The ASUKA (Advanced Semiconductor through Collaborative Achievement) — Asuka was an ancient metropolis in Japan — project targets 100-70nm SOC device design and process technologies development. When Selete (Semiconductor Leading Edge Technologies Ltd.) moves from Totsuka (Yokohama) to the Tsukuba Cleanroom in April 2002, it will be in a position to drive project activities.
The facility is being constructed and operated by the National Institute of Advanced Industrial Science and Technology (AIST) — Japan's largest public research entity. The organization's members represent some 15 research institutes. The Semiconductor Technology Academic Research Center (STARC), although an independent organization, has joined ASUKA. Key processes being studied include transistor module integration with high-k technology, and BEOL (back end of line) integration with Cu and low-k integration.
The MIRAI (Millennium Research for Advanced Information Technology) — mirai means "future" — project is dedicated to 70nm (and beyond) process technology and will be ongoing until 2007. Activities are focused on such issues as high-k and low-k integration, new transistor structure development, and technologies for circuit design and lithography masks.
This project is particularly innovative due to a policy that ASRC director, Dr. Masataka Hirose, developed in conjunction with leading-edge technology and world-class resources. Japan's national projects used to be open only to Japanese companies; yet of the 25 companies in the semiconductor industry and the AIST currently involved in MIRAI, there are two that are not headquartered in Japan: Intel and Samsung Electronics.
The HALCA (Highly Agile Line Concept Advancement) minifab project is predicted to reduce emissions by 60% through the development of multipurpose tools [2]. Officially, the HALCA project began in 2001 under the leadership of Dr. Ohmi of Tohoku University, with equipment installed at tool suppliers' facilities including Tokyo Electron Limited (TEL), Ebara, DNS and Ulvac. Most of the tools will be moved to a Tsukuba super-cleanroom in April 2002. The main objective of this project is to reduce total energy consumption of semiconductor fabs by 60%.
In addition to the efforts of Ohmi, HALCA was an outgrowth of the activities of its vice director, Dr. Katsuya Okumura, whose initial concept of a minifab was formed while he was at Toshiba. In 2001, he moved to Tokyo University and began working with TEL, Ebara, DNS and Ulvac — companies that had already begun work on the technology — to develop the idea.
The total HALCA project budget will be about eight billion yen for three years, with the Japanese government (METI: Ministry of Economy, Trade and Industry) expected to subsidize the project to the tune of about two billion yen. Ten member companies will cover the remaining budget of up to six billion yen. Participating device manufacturers include Toshiba, Sony, Sharp, Epson, Rohm, and Sanyo (on an independent basis).
 Figure 1. Example of HALCA project objectives using a typical CMOS logic device (130nm). (Source: ASET/T. Tsumori, SEMI Technology Symposium, Dec. 2001) |
The project has nine main objectives, with advanced logic device manufacturing (in a minifab setting) being one of them (Fig. 1) [2]. Key requirements for minifab tools include versatile process chambers and shortened raw process time (RPT). (As defined by HALCA, RPT is equal to the sum of the theoretical process time, lot load and unload time, pilot wafer process time, and lot link and quality control time.) Some tools can cover sequential processes in the same chamber, eliminating wafer-transfer time and idling time.
Mini Vs. mega
In general, semiconductor device manufacturing and its supporting equipment tool sets have been designed for high-volume production — the so-called mega-fab approach. Implementation of the mega-fab has led to manufacturing cost reductions that enabled the expansion of the consumer products market; its greatest merit is scalability. Though it depends on the number of wafers processed, tool availability is relatively high, which means that short cycle-time manufacturing is possible. On the other hand, high-volume production requires a significant amount of investment.
In the past, Japanese device manufacturers focused on DRAM manufacturing, and a business model requiring high-volume and low-mix (little variation) products. The mega-fab effectively and efficiently produces these kinds of devices. The degree of change in the silicon cycle is increasing, however, and the requirements on the end-products that use semiconductor devices are also changing rapidly. Even for DRAM manufacturers, the specifications change frequently.
To tackle these challenges, Japanese device manufacturers have recently begun shifting from a DRAM to a "system LSI" business model. In general, the system LSI model employs both various volume levels and high-mix manufacturing and has been discussed for the last three to four years. Tool development started about two years ago at the behest of Toshiba.
The minifab is a small production unit for device manufacturing that can be built quickly enough to meet market needs. While the large investments associated with mega-fabs sometimes cause overcapacity in the market, the minifab concept appears to minimize the gap between supply and demand. Key attributes of a minifab include: less investment, rapid ramp-up, low-volume manufacturing, decreased energy emissions, and low-cost manufacturing.
The term "minifab" does not signify small size; rather, it is meant to connote flexibility and agility. The tools that run in a minifab will not be the tools found in current fabs. Furthermore, lower throughput and lower price will not be the key factors. Instead, device manufacturers will reduce the number of tools used for low-volume production, thereby lowering investment costs. It is difficult, though, for a minifab to maintain the same cycle-time as that found in the mega-fab. This is because the actual tool utilization in a mega-fab is relatively low, so many tools are required to meet specified production levels. Lower utilization can translate to shorter cycle-times [3]. In general, the mega-fab's cycle-time is shorter than that of the minifab.
 Figure 2. Fab tool overcapacity. (Source: ASET/T. Tsumori, SEMI Tech Symp, Dec. 2001) |
If the minifab concept were implemented with current tool sets, it would not be cost-effective because most have excess production capacity (Fig. 2), translating to excess investment. Additionally, the power consumption (kWhr/lot) of mega-fab tools used in a minifab setting is 1.5¥ higher than that of a mega-fab with the same wafer starts (Fig. 3). It is therefore necessary to develop new tools for the minifab [4]. For example, a tool in which one process chamber can function for multiple processes is versatile. This is one of HALCA's approaches, in addition to reduced investments and cost-effectiveness.
 Figure 3. Comparison of electric consumption. (Source: ASET/Y.Mikata, JST Forum, May 2001) |
HALCA projects
Toshiba Semiconductor and TEL have developed a new fast thermal process system, the TELFORMULA, which has a batch size of 25 wafers (Fig. 4). Conversely, the batch size of conventional thermal systems is 100-150 wafers, and the standard RPT is about 4-5 hours, which causes queuing time in front of batch systems and increases device manufacturing cycle-time.
 Figure 4. RPT of TELFORMULA (SiN). (Source: TEL/M. Yamaguchi, JST Forum, May 2001) |
The new tool can shorten RPT by applying a newly developed heater and intelligent thermal control system. Using a simulation model, it has been calculated that cycle-time can be shortened because of a smaller batch size and because the wafer pod is used as the transportation container in the cleanroom [5]. (Since a wafer pod carries 25 wafers at once, a 25-wafer batch tool does not affect fab-level cycle-time.) It is also compatible with that of a single-wafer thermal system [6]. Having multiple functions is key to realizing the minifab concept. Since this new system has a wide operational temperature area and can stabilize temperatures within 2.5 min, different recipes can be run sequentially without reloading the wafers (Fig. 5).
 Figure 5. Elimination of process steps using a sequential process. (Source: ASET/Y.Mikata, JST Forum, May 2001) |
Toshiba and Ulvac have co-developed a direct ion beam implant system using a stencil mask [1]. This system implants ions chip-by-chip through a stencil mask, allowing the elimination of patterning steps during the doping process. The implanter has a stage, supplied by Nippon Seiko, similar to a stepper's. Using this technology, one can eliminate processes such as resist coating, lithography, develop, inspection, and ashing. The results are a shortened cycle-time, lower process costs, less capital investment, and a minimization of cleanroom space. Increasing stencil mask lifetime by doping nitrogen into it is currently being investigated.
The chemicals used in an etching process will etch the inner wall of a process chamber, so, typically, such a system is set up for a dedicated process. But to save on hardware costs, an etching system in a minifab has to be able to perform several processes. The keys to efficiency are the dry cleaning process and the initializing (seasoning) technology. To meet these requirements, Toshiba and TEL have been co-developing dry cleaning technology for an etching system that can run several processes. It is necessary to initialize the process chamber and implement a seasoning process, but it is expected that costs overall will be lower using this approach. The key factor will be how rapidly the system can switch from one process to another, making it possible to reduce the number of etching systems in a minifab. The HALCA project target is to reduce the number of etching systems from nine to five. In situ gas cleaning technology and new materials for chamber walls are also being investigated.
Another one of the HALCA project's objectives is to minimize energy emissions from semiconductor fabs, so a recycling gas system is being developed for the etching system. Once gas from the etcher is pumped out of the system, it is collected in an exhaust line to be used again. The gas returns to the process chamber through a bypass line located at the exhaust line. A filtering system is incorporated into the bypass line. Using this system, the process performance of etching remains acceptable, and further efforts to minimize gas consumption are being investigated.
Toshiba and Ebara are working together to develop an immersion copper plating system [1]. A porous ceramic plate is placed just below the anode electrode, forming a uniform electric distribution and a uniform copper layer. Since the anode electrode is very close to the wafer, it can minimize the volume of the plating bath. Consumption is expected to be about one-tenth that of current systems. The cleaning and drying processes are implemented in the same area, allowing the tool footprint to be about half that of traditional tools.
A scan coating technology for low-k interlayer dielectric coatings has also been developed with the goal of reducing emissions. Although the project is now a part of HALCA, it was started by Toshiba and TEL. While a spin system typically wastes about 90% of coating materials, the scan system utilizes over 90% of the coating material. Thus, coating material consumption for the scan system is about 1/10 that of the spin system (see table). Scan technology is expected to replace spin-on dielectric (SOD) processing, whether in mega- or minifabs. (Most of the technology being developed in HALCA projects can be applied to both mini- and mega- fabs.)
With a minienvironment system, space used in a minifab cleanroom would be dramatically reduced. Because all minifab tools would be installed in the same area, however, it would be necessary to control chemical contamination. Closed carriers are currently used in cleanrooms, but they do not eliminate cross-contamination. Toshiba and Ebara are investigating a closed type pod that has a ULPA filter and a chemical filter on it. A fan motor circulates ambient air inside the pod, and the pod has a battery that charges while the carrier is placed on the loadport of each tool. It is not necessary to run the fan all the time, only periodically, and the battery lasts for a few days. This is an active cleanroom system, so, as expected, it contributes to a reduction in operating costs.
Minifab issues and challenges
It is expected that the investment costs for a minifab will be about 45% less than those for a conventional mega-fab, and though the required amount of investment for a minifab is low, costs can increase if the device manufacturer tries to expand the facility. In this case, the cleanroom concept should be revisited. In particular, the facility system design has to be carefully considered. Mega-fabs tend to require additional specifications that address factors such as air intake, exhaust, electric supply and water supply, etc. The minifab is expected to minimize these specifications. Also, the minifab layout is based on being able to connect each tool and facility more easily — an issue that needs investigation and collaboration with the fab construction company.
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Another consideration that affects the reasonableness of adopting the minifab is that the minimum production target of such a facility is 100 lots/month. This means that chip output, as well as sales revenue, may be low. Of course, it depends on the products (devices) being manufactured. However, because the ratio of sales costs and other overhead costs seems to be high, the overall business model is a critical issue for the minifab strategy. The concept should be seen as leverage to improve business strategy, where appropriate, and not as an end in itself.
Dr. Okumura has asserted that real-time lot tracking and management via simulation software should be used in a minifab [7]. Implementing such a methodology would make it possible to reallocate production lots in real-time. Because production lots would be rather small, it is possible to manage them using a real-time simulator to achieve controlled lot input to the fab and improved cycle-time.
Okumura has also indicated that an intelligent fab management system can minimize facility specifications, which, for the mega-fab, are usually an accumulation of the maximum requirement of each tool, thereby inflating the end result. Intelligent fab management systems control each tool's status and shift the peak of facility usage — a concept that can be applied to the management of electric power, DI (de-ionized) water, exhaust gases, etc.
Conclusion
The minifab is not a magic remedy to solve all the manufacturing problems currently facing the semiconductor industry. Rather, it is important to design such a fab based on each company's business model. To be effectively implemented, hardware (tools and facility), operating software, and business strategy must be taken into account. It would not be effective to introduce the minifab business model to every manufacturing line. It does, however, have the potential to make some semiconductor manufacturing business models more cost-effective and efficient, and should be given serious consideration.
References
1. K.Okumura, Y.Mikata, et al., "Toward the Agile Fab," Nikkei Microdevices, March 2001.
2. Toshirou Tsumori, "The Object of HALCA Project," presented at Semi Technology Symposium 2001, Makuhari, Japan.
3. D.P. Martin, "The Advantages of Using Short Cycle Time Manufacturing (SCM) Instead of Continuous Flow Manufacturing (CFM)," ASMC98 Proceedings, pp. 43-49, 1998.
4. Yuichi Mikata, "QTAT Manufacturing and Vision for Future," JST Forum, May 2001.
5. Mitsuyuki Yamaguchi, "Solution for Short Cycle-Time Manufacturing," JST Forum, May 2001.
6. Y. Hayashi, Y. Kodashima, M. Yamaguchi, "Semiconductor Equipment Design for Short Cycle-Time Manufacturing," Future Fab International, Issue 10, 2000, pp. 130-134.
7. K. Okumura, K. Mitsutake. "The solution is the Agile Fab," Nikkei Microdevices, Nov. 2001.
Mitsuyuki Yamaguchi received his BS degree from Tohoku University and is now senior manager of corporate marketing at Tokyo Electron Limited, [email protected]; ph:81/3-5561-7138.