Recipe for qualifying processes at a pure-play foundry
04/01/2002
by Thomas Choi, Senior VP of Technology, Dongbu Electronics, Eumsung, Korea
Teamwork and concurrent engineering techniques played a key role in achieving a qualified production process at Dongbu's Class 1 wafer fab in Eumsung, Korea (Fig. 1). The work was concluded within three and a half months after incorporating Toshiba's advanced 0.25μm mixed-signal CMOS process. The initial wafers, consisting of a mix of logic, analog, and memory functions, completed the industry-standard qualification burn-in test and posted die yields over 80%.
 Figure 1. Dongbu Electronics' Fab-1, Eumsung, Korea. |
More than 20 vendors supplied equipment (see table). Most of the sophisticated systems for photolithography, diffusion, etching, and thin-film production were provided by Nikon, Applied Materials, and Tokyo Electron Ltd. The most complex production tool was a metal plasma etcher, which required special care to control corrosion and polymerization.
Dongbu, with Toshiba's support and encouragement, opted for an "exact copy" approach in its qualification efforts, mirroring Toshiba's wafer fab in Oita, Japan. By duplicating the equipment suite at the Oita fab, cost efficiencies were realized and the stage was set to qualify the process modules quickly. The execution plan for the qualification process called for the maximum use of concurrent engineering. Additional leverage was gained from the equipment vendors who worked over several shifts, including weekends, to support the parallel engineering drive.
Driving concurrent engineering
Dongbu's task force of 59 technologists worked closely with Toshiba's Technology Outsourcing Group. Effective application of concurrent engineering techniques requires an understanding of key tasks and identifying challenges and constraints. Once these factors were determined, a concrete picture of which tasks or events can be processed in parallel was used to prepare a backup plan. Key elements of the plan (Fig. 2) drove simultaneous engineering activities and incorporated the following elements: comprehensive collection of baseline data, partitioning and alignment of major tasks, scheduling and allocation of resources, simulations/emulations, and teamwork.
 Figure 2. Concurrent process set-up plan. |
To facilitate baseline data transfer, documents from Toshiba were categorized into 12 technical groups, which were reviewed by core members representing each technical area in Dongbu's transfer team. A list of key tasks, sub-tasks and additional documents required from Toshiba was prepared. Toshiba experts then performed intensive on-site training for each of the teams over an 11-week period. Workshop meeting minutes — as well as those collected during the many group meetings held to share the information collected from the on-site training and other reports — were edited into a handbook. Toshiba and Dongbu also held joint meetings with various vendors to understand clearly the tool requirements, delivery and setup issues.
For process qualification to proceed expeditiously, it was important for the Dongbu-Toshiba team to understand clearly what goals were to be achieved (e.g., set up several technologies within shortest time) and how they would be executed. A number of major tasks needed to be clearly defined, as well as an effective concurrency and alignment scheme designed around these tasks to meet the goals of the project.
For example, both core logic and analog processes were chosen to be set up in parallel. The core logic processes were partitioned into five major process modules, and the analog processes into four. The front end of line (FEOL) and back end of line (BEOL) were chosen to be processed in parallel during the process module set-up stage and to be integrated during the qualification stage.
Careful scheduling and allocation allowed for smooth execution by taking into account all the practical issues the team was expected to face. Detailed engineering events or activities for each major task were identified, and detailed action plans for both best- and worst-case scenarios were prepared by a working group for each major task. A higher-level working group identified misalignment between tasks and events, and several loops of reiteration were performed. Contingency plans were also prepared for all high-risk processes. For example, use of Toshiba-processed wafers was taken into account when some equipment delivery or set-up could not be well aligned with others.
Emulations and simulations helped identify the potential problems along the critical paths in the execution plans, as well as providing a chance for all participants, including inexperienced operators, to familiarize themselves with the execution processes. An emulation program to run a virtual fab operation was prepared and all level of participants (engineers, technicians and operators) took part through Dongbu's intranet.
Several scenarios were inserted during the virtual fab operation to evaluate the effectiveness of operation flow and participants' reactions. All the problems observed during the simulation exercises were recorded, reviewed, and corrected. A second round followed to allow the participants to have a higher level of confidence.
In order to execute major tasks concurrently, many activities had to be interwoven so neatly and tightly that any mistake or miscalculation might delay or damage operations. To minimize confusion, workshops were conducted to explain the project missions, the overall features of the process technologies, the detailed set-up plans, the standard work procedures, and workmanship. The sessions were held numerous times during the set-up period. Additional meetings were held twice daily during the week, and once a day on weekends and holidays, to monitor the progress and realign multiple events accordingly. Various events to build up intra-teamwork and inter-teamwork were also held.
Although not designed to be part of the qualification process, the training of 39 Dongbu engineers at Toshiba's Oita fab over an 11-week period proved helpful. This on-site training armed the task force with useful information that expanded upon details not included in transferred documents. For example, the history of revisions during Toshiba's process optimization was reviewed during the on-site training. These kinds of exercises enabled the task force to understand historical processing issues, their causes, and resolution. These activities also contributed to better planning and facilitated the preparation of check lists for equipment and process acceptance, to define potential failure modes and defect types, and to set up critical in-line quality control items. The training enhanced communications flow between the two companies. This allowed a rapid response to unforeseen difficulties during set-up.
Engineering challenges
During the effort to qualify the Toshiba process on newly installed production equipment, several engineering challenges had to be met: 1) coordinating timing of equipment delivery and installation with the set-up process, 2) assuring quality and reliability levels before starting qualification lots, and 3) complying with Toshiba's strict qualification criteria.
Coordinated timing of equipment delivery, installation, and process set-up was vital because each module set-up required a set of different equipment, including not only process tools, but metrology and analysis tools as well. Furthermore, many modular activities were running in parallel. Workshops were especially helpful in aligning these efforts, as it was important that participants understood the overall project execution plan and how their activities were intertwined with others. This minimized schedule and set-up conflicts with other module teams and ensured that all work flowed smoothly and concurrently.
Workshops were held three times during this period: once before project kickoff, again during the early stage of core logic process setup, and lastly at the beginning of the analog process setup. In the end, participants clearly understood their roles and how to align and compromise with members of other module set-up teams when an unexpected conflict or delay occurred.
To provide quality and reliability assurance before starting qualification lots, extensive physical and chemical analyses (physical profiles, impurity concentration, electrostatic damage, etc.) were performed on all equipment and unit processes and compared with data obtained from Toshiba. Whenever possible, modular level reliability items such as gate oxide integrity, hot carrier immunity, and electro-migration were monitored. Qualification criteria encompassed testing for metal integrity, oxide integrity and transistor reliability, as well as demanding test conditions performed on large sample sizes.
Qualification of the various process modules was supported by the correlation of metrology tools with those used in Toshiba's Oita fab. Metallic contamination and electrostatic damage were checked on all the new equipment, including the metrology tools during the process set-up. While such correlation and checking is typically performed only on selected equipment to minimize engineering efforts, complete correlation and checking were done on all the equipment in cooperation with Toshiba engineers. While this required a large amount of engineering effort and time, such exhaustive efforts allowed the elimination of engineering reiteration caused by mismatching problems associated with the process and metrology tools. By correlating Dongbu's equipment data with those of Toshiba, baseline processes could be quickly established. This approach helped meet the aggressive qualification schedule.
Overcoming scheduling difficulties
Simultaneous engineering efforts were facilitated via a virtual fab that was created using simulation software for certain processing steps and an intranet connection between the two companies. The set-up enabled the emulation of critical processing steps before the actual processing of real silicon. Accordingly, it was possible to check whether the concurrent modular plans were executable without conflict, and how well the team participants were prepared.
Using the virtual fab, processing problems were intentionally set up to monitor how quickly and effectively the team would react, as well as what impact the problems would have on schedule tracking and the effectiveness of contingency plans. These exercises highlighted the need to define certain procedures more clearly, such as those relevant to scrap
eject
ework. Also uncovered were contention issues during packaging
eliability testing as multiple process modules competed for system priorities.
Even though the set-up of certain new process tools was delayed from the targeted schedule, the concurrent development and integration of process modules through the use and correlation of both Dongbu-processed and Toshiba-processed wafers was accomplished. Process and failure analysis tools were set up on schedule and contributed to the engineering efforts. To effectively identify and troubleshoot a process-related failure, a software program package for systematic failure analysis developed at Toshiba and modified at Dongbu was applied. This package predicted which physical layer might be problematic by using only electrical testing data. Figure 3 shows examples of the failure mode observed using the software package during the qualification process.
 Figure 3. Examples of failure mode analysis a) Pareto analysis; b) root cause. |
Faced with a delay in the delivery of its new lithography system, Dongbu temporarily applied alternative tools to initiate the set-up of Toshiba's process module. Unfortunately, these tools proved unstable during operation, and posed a danger of delaying the total process module set-up procedure. To minimize this impact, they were operated off-line in a controlled minienvironment at the expense of reduced throughput. In parallel, Dongbu worked closely with its photolithography equipment vendor to accelerate the set-up of the new system once it was delivered.
Conclusion
The combination of teamwork and effective deployment of parallel engineering techniques enabled Dongbu to achieve the rapid qualification of its advanced CMOS processes. Among the key factors that contributed most to the execution of multiple tasks were:
- comprehensive collection of baseline data,
- prudent partitioning and alignment of major tasks,
- careful scheduling and allocation of resources,
- simulations/emulations to identify potential problems, and
- teamwork and intra-team communications.
The achievements of this initial engineering effort gave impetus to the drive to qualify Toshiba's finer 0.18μm process — as well as foundry-compatible CMOS processes at both 0.25- and 0.18μm linewidths. A benefit of the module-based concurrent engineering approach is that the equipment and process module platforms that were finally implemented are reusable. Indeed, many aspects of the methodology that were used to set up, characterize, and accept the process modules are directly applicable to next-generation technologies and their derivatives. If a new module is necessary, it can be developed and certified at the module level prior to its integration with the existing modules.
The 1000-hr qualification of foundry-compatible 0.18- and 0.25μm processes, as well as the Toshiba-licensed 0.18μm process, was completed by the end of 2001. The 0.13 μm process should be available during the third quarter of 2002. Also, the Fab-1 facility is expected to be able to ramp up to a total monthly output of 45,000 wafers in early 2003. The campus can accommodate the construction of six additional wafer fabs to meet increasing future demand.
Thomas Choi received his BS in electrical engineering from Seoul National University, Korea, and his MS and PhD degrees in electrical engineering from the University of Michigan, Ann Arbor. He is currently leading R&D activities as a managing VP at Dongbu Electronics Inc., 471-1 Sangwoo-ri, Kamgok-myun, Umsung-kun, Chungbuk, 369-852 Korea; ph 82/43-881-8695, fax 82/43-879-9911, e-mail [email protected].
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