New barrier layers can help Cu/low-k integration
03/01/2002
 |
Overview
The importance of copper and low-k thin film materials in next-generation interconnect structures is well established and the process of integrating these materials into manufacturing is progressing rapidly, particularly with copper film technology. However, a consistent industry-wide focus to minimize the k values of new dielectric materials and then force-fit them into back-end-of-line interconnect manufacturing flow with traditional plasma oxide (SiOx) integration schemes has slowed overall integration progress. A bridge is needed to assist in the industry transition from the traditional "dense" dielectrics to low-k dielectrics. Amorphous hydrogenated silicon carbide (a-SiC:H) films may provide that bridge.
Interconnect back-end-of-line (BEOL) processing of silicon ICs has evolved from subtractive aluminum, where the interlayer dielectric (ILD) consists of oxides applied over existing patterned metallization, to copper dual damascene processes where metal is inlaid into patterned dielectric layers and undergoes chemical mechanical polish (CMP) to complete conductor isolation. Dual damascene processes were developed to facilitate patterning of the copper conductors and to meet the geometry demands for shorter circuit delays and smaller transistor dimensions. These growing requirements have now dictated that low-k dielectric films be integrated into the damascene process to optimize interconnect performance. More than with subtractive interconnect technology, damascene processes place large demands on dielectric material integrity, such as requiring greater control of CMP erosion, withstanding more aggressive cleaning approaches, and minimizing metal diffusion.
 Figure 1. Applications of the barrier/hard mask/etch stop dielectric in Cu dual damascene interconnection technology. |
Damascene process evolution has resulted in the use of several dielectric layers to address the integration and capacitance requirements associated with the structure. The first is the primary isolation ILD. A second layer, known as the barrier/hard mask/etch stop film, is stacked on the ILD to provide a block for copper migration and act as a dry etch mask, CMP polish stop, or embedded dry etch stop, depending on the structure (Fig. 1). Plasma silicon nitrides (SixNyHz) were originally used as the barrier layer with SiOx as the primary dielectric, but the relative permittivity of these nitride dielectrics is high (6<kGlt;8) and limits the ability to reduce electrical delay within the interconnect. To reduce interline capacitance, the ILD layer can be switched from SiOx to low-k dielectric materials, but even in this case, the silicon nitride layer limits capacitance reduction and opens other integration difficulties in the damascene patterning process. Clearly, a different material is needed for the barrier, one that can meet the diffusion barrier requirements, improve selectivity in patterning processes, maintain electrical integrity through low leakage and good breakdown strength, and at the same time provide a relative permittivity that is lower than nitride. Amorphous SiC:H is filling these requirements because of its more desirable mechanical, chemical and electrical properties compared to oxide and nitride films.
Low-k integration requirements
The basic unwritten rule for low-k materials is that, for a given application, they should integrate no differently than SiOx films. The key integration points are as follows:
- Chemical integrity. The material must not degrade chemically in order to maintain its permittivity, resistivity, and film thickness during patterning and cleaning processes; and
- Mechanical integrity. The material must have controllable polish properties, show good adhesion to contacting films, and enough mechanical strength to ensure film integrity in subsequent processes all the way through packaging of the final product.
Low-k materials are relatively porous and/or soft, and commonly contain methyl and hydrogen bonds, making them vulnerable to chemical breakdown in subsequent process steps. They provide the capacitance reduction for shrinking dimensions used in metal conductors but are often poor barriers against Cu+ drift. These ILD films need to be protected to maintain their beneficial electrical properties.
One method to overcome some of these problems is the selection of a robust barrier dielectric material that can provide the mechanical integrity to the interconnect structure while at the same time protecting the underlying ILD material from degradation in subsequent process steps.
Barrier/etch stop requirements
To provide the mandatory electrical performance in the interconnect structure, any barrier/hardmask material must be insulating and enable the fabrication of interconnects with low capacitance and low power dissipation in order to achieve optimum signal performance in next-generation high-speed circuits. To achieve adequate reliability, the films should also exhibit sufficient dielectric strength and impede Cu+ diffusion at electric fields of approximately 1MV/cm. Low-k spin-on dielectric (SOD) and PECVD films have significantly lower mechanical strength than SiOx. To integrate these low-k films successfully in interconnect structures previously designed around more mechanically capable films, it is helpful to sandwich them between other "capping layers," which have higher modulus and hardness. This will improve the performance of the structure in subsequent CMP processes, and later, in final packaging.
As with any dielectric, the cap material must be stable, both to thermal cycles and chemical-based cleaning. Most low-k films are hydrophilic. If the ILD material contains or picks up moisture, and/or is susceptible to mobile ion contamination, the cap should act as a barrier to impede the movement of these charged entities. For this reason, capping of low-k films is often performed directly after ILD deposition or after a short ILD anneal step.
The barrier material must be thermally stable, remaining unchanged at normal Cu damascene processing temperatures of 300-425°C. Outgassing of the barrier or ILD layer during metal barrier (Ta or TaN) or Cu seed deposition will ruin the metals' conductivity. The barrier dielectric material must exhibit good adhesion to the metals in order to withstand the stresses generated as a result of the coefficient of expansion mismatch between the conductors and insulators. Stress changes in the barrier film resulting from thermal cycling can lead to adhesion failures and cracking.
The process chemistry used to deposit barrier films must minimize particle and pinhole formation. Such problems can lead to such failures as dielectric undercut, bowing, and void formation during subsequent CMP and cleaning steps.
In the realm of photolithography, the hard mask must be compatible with photoresist deposition and strip processes. Photoresist is typically consumed during the etch process or removed afterward with plasma processing. If the resist is consumed during etch, the barrier layer will then be subjected to harsh etch chemistries. Therefore, good selectivity with respect to the ILD is required. Throughout this process, the barrier film must not change chemically in a way that adversely affects electrical performance.
Since available low-k films have k values <3, the relative permittivity of the barrier should be <5 in order to maintain optimal electrical delay characteristics [1]. Hence, interconnect capacitance levels with effective dielectric constants <3.8 can be easily achieved.
Amorphous-SiC:H has low relative permittivity, tunable between 4 and 6 depending on deposition parameters, and good standard thin film characteristics such as adhesion, chemical and moisture resistance, and mechanical strength [2-4].
Lithography
With the size of the lithography targets shrinking, DUV photoresist is mandatory. Since substrate reflection increases as the wavelength decreases, and most low-k dielectric films are transparent at DUV wavelengths, it is necessary to add an anti-reflective coating (ARC) either underneath or on top of the photoresist to minimize reflection [5]. The addition of a spin-on ARC layer can complicate the etch process, however [6]. If the barrier/hardmask material used in the dual damascene structure exhibits sufficient ARC properties, though, the ARC layer can be eliminated. This is the case with a-SiC:H. Studies indicate that a-SiC:H is an effective inorganic ARC as well as a hardmask/barrier protective layer. Unlike SiO2, which is transparent at DUV wavelengths, reflectivity modeling yields a reflectivity less than 3%, with very good uniformity for a-SiC:H layers as thin as tens of nanometers (Fig. 2).
 Figure 2. DUV substrate reflectivity model for an a-SiC:H/low-k ILD damscene stack. |
Etching
Maximizing the selectivity of the resist to the barrier/hard mask layers and between the barrier and low-k ILD is essential to creating a process flow that yields straight sidewalls and controllable dimensions. Amorphous-SiC:H films are attractive for dual damascene processes because they exhibit slower etch rates than silicon nitride, SiOx, and low-k films. These relative etch rates translate into high selectivity between barrier and ILD materials. The slow erosion rate of the barrier also allows for more control of the etch profile of the ILD, as the masking property of the barrier will not deteriorate before the etching of the ILD is complete. If a-SiC:H is used as an embedded or bottom etch stop in dual damascene, it can provide a wider process margin, enabling better control to prevent the unintentional exposure of the metal contact at the bottom of the via during dielectric etch (punch through).
However, a-SiC:H is so chemically inert that it may be difficult to dry etch. If the appropriate resist process is not established, based on material, thickness, and post-exposure bake selection, a condition of low selectivity toward the photoresist can occur. If resist consumption during etch is intended, this is not really a problem, but if the process calls for resist to be intact after the hardmask is patterned, a dual hardmask approach can be utilized.
 Figure 3. DUV substrate reflectivity model for dual SiO2/SiC:H HM (structure shown right). |
In the dual hardmask approach, a thick layer of SiOx can be placed on top of a much thinner layer of a-SiC:H (Fig. 3). The resist and SiOx layer help to create a better etch profile in the barrier/ILD layers and the necessary ARC performance is provided. Additionally, the SiOx can provide two other important functions. First, since the chemical interaction between oxide and DUV resists is well understood, it acts as a controllable chemical interface for application of the DUV resist. Second, since the polish rates of oxide films are established, the oxide layer can act as a sacrificial CMP layer, allowing good control of the CMP removal process. The successful implementation of this dual hardmask approach ensures that a continuous a-SiC:H layer will remain on the low-k material after CMP, thus protecting the underlying ILD material properties.
Dry etch studies have been investigated for the single and dual hardmask/ILD etch. Several combinations of Ar, N2, O2, CHF3 and CF4 etch gases were tested to produce a process with minimized resist/hard mask erosion and maximized uniformity across the wafer, with good critical dimensional (CD) control. The single a-SiC:H hard mask approach with an Ar/CF4/CHF3/O2 etch chemistry showed adequate selectivity to oxide (3.5:1), resist (5.5:1), and a-SiCO:H (6:1) films. The process of opening a thick a-SiC:H hardmask (~200nm) was slow and consumed too much resist, however. By modifying the etch chemistry to Ar/CF4/N2/O2, an improved etch rate through the hardmask was achieved. Next, by combining the dual hardmask and etch approaches, using an Ar/CF4/N2/O2 etch to break through the mask layers then switching to an Ar/CF4/CHF3/O2 chemistry for the ILD, adequate selectivity was maintained throughout the etch of the entire stack, resulting in the production of vertical sidewalls with minimum deterioration of the profile at the top of the via/trench opening.
 Figure 4. Dry etch and strip results on dense 0.2 trenches (strip times are normalized fro removal of 200mm resist). |
Once an etch process is established, a resist strip/clean process compatible with the stack dielectrics must be identified. This is one of the most difficult steps in the integration of low-k materials. In one set of experiments, five separate strips were performed on 0.2μm dense and isolated structures (Fig. 4). Most of the strip processes yielded poor results for the underlying low-k ILD material (a-SiCOH), though none damaged the a-SiC:H hardmask. The best result for the low-k ILD strip process was obtained using a N2/O2 chemistry at a low temperature and pressure.
Copper polishing
For copper CMP, important issues include high polish rates, good across-wafer uniformity, and high selectivity to the CMP stop layer. An ideal stop layer has excellent adhesion to the underlying low-k layer, is erosion resistant, protects the ILD layer by providing a moisture barrier during subsequent cleaning processes, and blocks Cu+ migration.
Chemically inert a-SiC:H materials appear to provide a good CMP stop. Chemical mechanical polishing of a-SiC:H was performed on blanket wafers using Cu and Ta slurries. After a 120-sec polish, film loss was on the order of only 2-3nm. Amorphous-SiC:H films exhibited better adhesion than oxide and nitrides to some low-k ILD films. For example, adhesion of a-SiC:H to SiCOH ILD layers was evaluated with visual inspection following CMP.
 Figure 5. Normalized adhesion strengths by m-ELT. |
Figure 5 shows the test structure and adhesion results normal to oxide, where the cap and liner material sandwiching the SiCO:H ILD layer were changed among samples. Plasma oxide, nitride, oxynitride, and a-SiC:H were tested. Following CMP, no delamination was noted on a-SiC:H films; all others showed signs of delamination. This result was further quantified using modified edge liftoff testing (m-ELT). Here the dielectric stack samples were cryogenically cooled to induce large stresses at the film interfaces due to coefficient of expansion mismatch variations between the films. When the stress exceeds the adhesion strength, delamination occurs. The a-SiC:H film provided up to 4¥ more adhesion strength compared to oxide, nitride and oxynitride (Fig. 5).
 Figure 6. Moisture barrier properties SiO2 vs. a-SiC:H (on k ~2.0 SOG). |
As stated earlier, protecting the underlying low-k ILD materials by blocking moisture during subsequent processes is an important requirement of a barrier film for successful integration of porous low-k materials. Moisture barrier properties of a-SiC:H and SiOx capping layers were compared by measuring capacitance changes in damascene structures fabricated using a low-k SOD (k ~2.0) as the ILD. Electrical tests showed that over time, the oxide cap allowed the capacitance of the structure to increase due to the diffusion of moisture into the underlying porous oxide material. This is noted as a 30% relative increase in the permittivity of the test sample in Figure 6. Moisture absorption through the PECVD oxide was confirmed as the mechanism for capacitance change using FTIR analysis. In contrast, no measurable change in capacitance was noted when an a-SiC:H barrier covered the ILD. The presence of the a-SiC:H barrier enables the complete fabrication of damascene structures with porous oxides while maintaining the performance enhancements associated with ILD materials with k <2.5. The use of the a-SiC:H film as a substitute for nitride in structures fabricated with SiOx, FSG, and SiCO:H ILD materials (4>k>2.6) reduced capacitance on the order of 10-25% [1, 8].
Conclusion
There is growing interest in thin film a-SiC:H for easing some copper/low-k integration issues. Damascene structures were fabricated using a-SiC:H barrier and low-k ILD, demonstrating significant capacitance reduction when compared with similar structures fabricated using oxide and nitride layers [7, 8]. Whether one uses a CVD or SOD low-k ILD in the damascene approach, a-SiC:H films may enable faster integration of current low-k material and improve the possibilities for success with future porous dielectrics. Improvements in a-SiC:H materials are under way to reduce further their contribution to the interconnect capacitance and improve the performance of next-generation logic devices.
Acknowledgements
The authors gratefully acknowledge the advance of this technology through integration work performed at IMEC, as part of the Industrial Affiliates Program, Samsung Electronics, and Applied Materials.
References
1. P. Xu, et al., "BLOk — A low-k Dielectric Barrier/Etch Stop Film for Copper Damascene Applications," Proc. 1999 IEEE Int'l Interconnect Technol. Conf., p. 109.
2. M.J. Loboda, "New Solutions for Intermetal Dielectrics Using Trimethylsilane-Based PECVD Processes," Proceedings of the 1999 European Workshop Materials for Advanced Metalization, Oostende, Belgium 1999, published in Microelectronics Engineering, 50 (2000) pp. 15-23.
3. M.J. Loboda, "Applications of Organosilicon Gases in Plasma Enhanced Chemical Vapor Deposition of Low-Dielectric Constant Films," Proc. Advanced Metalization Conference, ULSI XV, MRS, 2000, p. 371.
4. W.D. Gray, et al., "Process Optimization of Trimethylsilane Deposited a-SiC:H and SiOC:H Dielectric Thin Films for Damascene Processing," published Spring 2000, MRS Proc. Symp. Low Dielectric Constant Materials.
5. T.S. Ravi, et al., "PEARL — PECVD Anti-reflective Layer for Sub-0.35μm Lithography," Novellus Systems Inc., 2000.
6. P. Singer, "Anti-Reflective Coatings: A Story of Interfaces," Semiconductor International, March 1999.
7. T. Gao, et al., "Integration of 3MS low-k CVD Material in 0.18μm Cu Single Damasc. Proc," Proc. Adv. Metalization Conf, ULSI XV, MRS, 2000, p. 33.
8. S.G. Lee, et al., "Low Dielectric Constant 3MS a-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process," Jpn. J. Appl. Phys. 40, pp. 2663-2668, 2001.
W. Douglas Gray received his BS ChE in 1987 at CSULB. For 14 years, he has worked in the semiconductor industry in process, applications, and materials research. He has worked as an industrial affiliate for Dow Corning Corp. at IMEC in Belgium, studying the damascene integration of a-SiC:H and low-k CVD and SOD films. Presently, he is a CVD specialist located at the corporate center in Midland, MI. [email protected], ph 989/496-5857, fax 989/496-5121.
M.J. Loboda received his MS-Applied Physics in 1985 at DePaul University, Chicago. He has published more than 50 papers in the areas of spectroscopy, microwave/high frequency electronics and thin film materials science. He is currently the leader of the Thin Film Technology Platform at the Dow Corning Corp., Midland, MI, which focuses on the development of novel thin film processes for electronics applications.