Technology News
02/01/2002
"Flat" technology for better optoelectronics
Building on earlier reported work, researchers at NASA's Glenn Research Center, Cleveland, OH, believe they have found keys to making more reliable wide bandgap semiconductor devices used in optoelectronics, such as the blue and green LEDs used in stadium and building displays. Improved devices may also find wide use in more efficient and compact power control equipment, and short-wavelength, wide bandgap lasers could greatly improve the capacity of consumer products such as DVDs.
Previously, this research group developed a method for growing atomically flat surfaces on SiC wafers (see Solid State Technology, July 2001, p. 36). Now, the group has increased the size of the flat areas they can grow and have improved their method of heteroepitaxy (the process of growing layers of one material on a substrate of another). Scientists from Ohio Aerospace Institute in Cleveland and the State University of New York, Stony Brook, have also participated in this research.
The earlier work tended to grow silicon carbide crystals laterally beyond the targeted die-sized mesa edges, forming thin cantilevers. Continued development of this method shows that the cantilevers grow together to form a web covering the entire area between mesas with an atomically flat surface (see figure). "This web growth process allows atomically flat material to be grown over areas in wafer material that contain inherent defects like screw dislocations," says research team leader and Glenn Research Center engineer Philip Neudeck, who spoke recently at the International Conference on Silicon Carbide and Related Materials 2001 in Tsukuba, Japan.
With the improvement in heteroepitaxy, the team can grow a thin film of the cubic crystal form of silicon carbide (3C-SiC) on mesas of the hexagonal crystal form of silicon carbide (4H- or 6H-SiC). Briefly described, the researchers first flattened hexagonal silicon carbide mesas. Then, by careful manipulation of temperature and crystal nucleation rate, they deposited a film of cubic silicon carbide on the flattened mesas.
Neudeck says, "The films formed not only were free of defects that might have propagated from defects in the substrate, but also were free of planar defects, that is, defects in the order [stacking faults] or the alignment [double positioning boundaries] of crystal planes. Our work shows that, for cubic silicon carbide films, too rapid crystal nucleation in the early stages is the likely cause of planar defects."
The team will continue its work using step-free surface heteroepitaxy with other wide bandgap material films on hexagonal silicon carbide. "If we can produce defect-free films with these other materials, then industrial fabrication of a wider range of much improved wide bandgap devices is possible," Neudeck said. — P.B.
Carbon nanotube transistor circuits
The versatile carbon nanotube has been the poster molecule for nanotechnology. Now, Adrian Bachtold, Peter Hadley, Takeshi Nakanishi, and Cees Dekker of Delft University of Technology in the Netherlands have reported fabrication of multigate circuits that employ individual semiconducting nanotubes as field effect transistor channels (Science, 294, pp. 1317-1320, Nov. 9, 2001).
With a room temperature gain of >10, these enhancement mode p-type FETs have been combined to form such logic elements as a NOR gate, SRAM flip-flop and even a three-transistor ring oscillator. However, the high source-drain resistance of the open channels (>80kW) required high impedance circuitry, and parasitic capacitance limited the speed. The ring oscillator, for example, ran at 5 Hz!
 A single nanotube transistor with an aluminum gate. |
The secret to fabricating nanotube logic is to prepare a substrate with the ~500nm wide gate electrodes deposited first and expose it to air to form a nanometer-thick layer of Al2O3 insulator. Nanotubes are then dispersed on the wafer from a dichloroethane suspension, and an atomic force microscope is used to find sites where individual 1nm diameter nanotubes lie on top of the gates. Electron beam lithography is then used to delineate the sources, drains, and interconnects around the selected nanotubes. Finally, gold is evaporated directly onto the nanotubes and gates to make connections (see figure). Because the aluminum is already insulated with oxide, the gold connects only to the 100nm-long nanotube channels. The various gates on the wafer were individually addressable, in contrast to previously reported back-gate geometries.
The thin gate oxide allowed strong electrostatic doping of the nanotubes. The doping could be changed from p-type to n-type by changing the voltage, but p-type operation was used for the circuits described. Changing the gate voltage from -1.0 to -1.3V changed the current from ~0 to 50nA, with an on-off ratio of >105. All the devices had resistor-transistor logic using off-chip load resistors (R>100MΩ) and -1.5V bias voltage, with ~0V being a logical zero and -1.5V a logical 1.
Among the circuits described were a single transistor inverter, a dual transistor NOR gate, a two-transistor SRAM flip flop with a hold time >70sec, and a three-gate ring oscillator. The 5Hz frequency of the oscillator was determined by the 100pF parasitic capacitance of the wires connecting the off-wafer bias resistors to the transistors and the gigaohm resistance of the inverters. While on-chip resistors can reduce the capacitance by orders of magnitude, something else will have to be done about the device impedance. Lower contact resistance would help, but the quantum of conductance for a single-channel device (2e2/h) implies that each nanotube will have a min. resistance >13kW. Another problem is positioning the nanotubes at the desired locations, but recent progress in growing and placing nanotubes purposely may show ways to overcome those difficulties. The era of nanotube logic may be beginning. — M.D.L.
Intermediate rinse improves post-etch via cleans
Post-etch residue removal using a fluoride-based semi-aqueous chemistry (SAC) has shown improvement over industry-standard, hydroxylamine-based (HDA) processing. In a joint study by FSI International, Chaska, MN, and EKC Technology, Hayward, CA, and headed by FSI's John Diedrick, an intermediate DI water rinse added between two chemical dispense steps effectively removed post-etch residue in <20 min of total processing time at room temperature, compared to 40 min at 75µC in a typical HDA process.
 Top: Initial condition after via etch and ash process. Middle: Continuous single dispense step. Bottom: Dispense inse/dispense process. |
The benefits of fluoride-based processing — such as the need only for DI water rinsing compared to a two-step, alcohol or buffered solution/DI water rinse needed for HDA-based chemistries — make it a desirable alternative. Conventional post-etch residue removal methods have not been effective for fluoride chemistries, however. Typically, the wet chemical cleaning process is optimized separately for cleaning and rinsing, first to remove residues with an active chemistry and then to rinse the chemistries and reaction by-products. While straightforward, this approach does not completely remove post-etch residue when fluoride-based chemistries are used.
Fluoride-based chemistries diffuse into the post-etch residues, converting them into smaller, water-soluble subspecies. But because of the low water content in the chemistry, only a small portion of these "subspecies" is dissolved. Most of the undissolved residual subspecies remain in place until the DI water rinse step. Unless rinsing is thorough, however, some of the residual molecules will persist and form a layer of deposits, blocking residue removal. The intermediate rinse introduces large volumes of fresh water into the chamber, dissolving the subspecies and washing them away, thereby exposing the remaining post-etch residues. The chemistries can now diffuse unobstructed, cleaning at the same rate as before. Compared to HDA-based processing, fluoride-based chemistries with an intermediate rinse can reduce overall processing times by 30-50%, noted Diedrick.
In this study, wafers containing vias were etched and ashed. The polymer is raised up from the bottom of the via, the result of back sputtering and redeposition of eroding photoresist during the plasma etch (top SEM). The bulk of the photoresist is removed in the ashing process, leaving behind polymer residue, a mixture of inorganic aluminum and titanium metal oxides, silicon oxide, and remaining photoresist.
Half of the wafers were cleaned with a typical clean
inse/dry process with 5 min of continuous chemical dispense, and the other half underwent a recipe consisting of a two-step chemical dispense and an intermediate DI water rinse:
- 90-sec dispense (10 liters/min) of recirculated semi-aqueous chemistry,
- 30-sec chemical reclaim step, to reduce the interaction between chemicals and DI water,
- 30-sec intermediate DI rinse,
- 30-sec high-speed 500 rpm spin step to minimize water and chemical interaction,
- 90-sec dispense,
- 30-sec chemical reclaim step, to reduce interaction between chemicals and DI water, and high speed DI rinse.
Combining high spin and flow rates enabled a rapid turnover of solution in via openings. Deep trenches (4µm deep trenches (4µm deep x 0.5µm wide) were easily rinsed clean in <1 sec. Combining semi-aqueous fluoride chemistry with quick chemical dilution reduced potential for corrosion of aluminum/ copper metal at the via's bottom. The final rinse sequence focused on rapid solution turn-over in the via and the diluting and cleaning properties of a high-speed rinse. Rinse time was kept to a minimum to balance exposure of the metal at the via's bottom to the DI water with the necessary cleaning of chemicals from the process chamber.
Intermediate rinse cleaning process results were compared to the 5-min continuous clean. Though the chemical dispense time was longer, the continuous clean did not completely remove the post-etch residue (see middle SEM). In contrast, the intermediate rinse process removed all residue (bottom SEM), in less time and with fewer chemicals. Via dimensional gain, due to interlayer dielectric etch, was minimal. — R.D.