Key conference has major message: CMOS needed, still viable
02/01/2002
IEDM show Report
Pieter "Pete" Burggraaf, Senior Technical Editor
Looking for an application that will bring the IC industry out of its current slump? Consider the projected growth of broadband and, in particular, the microelectronics necessary to establish "residential gateways" and "simple-to-use home networks." "Estimates show broadband use growing worldwide from 12 million users in 2000 to 90 million in 2003," said engineer Johan Danneels from Alcatel Microelectronics, Brussels, Belgium, speaking at the 2001 IEEE International Electron Devices Meeting (IEDM), held December 3-5, 2001, in Washington, DC.
Associated with this, fiber optics connections are doubling every nine months, but the last mile, which includes residential gateways, is the bottleneck to better broadband use. Residential gateways are needed to manage shared Internet access for what Danneels eventually sees as "pervasive computing" — where a user is surrounded by computing devices (i.e., web pads, e-books, PDAs, set top boxes, personal video recorders, IP phones, game consoles, etc.) and smarter kitchen appliances.
"Today, we still think of an Internet appliance as a stripped down PC, but over time, even a dishwasher will become a simple Internet appliance that connects to a manufacturer's site for maintenance needs. In the near future in a home, more money will be spent on electronics than on [building materials]," he said.
Danneels believes that deep-submicron CMOS — not emerging alternatives that target replacing CMOS — and first-time-right system-on-chip (SOC) designs are essential to achieve residential gateways at the right consumer price and with the ability to hit market windows. "Standard CMOS is the only way to drive cost down quickly and aggressively, which is an absolute must," he said. In addition, SOC semiconductor companies must master digital, analog, rf, and high-voltage designs. Successful companies must rely on third parties; he sees silicon foundry megafabs, as well as research institutes, playing a large role in providing design and process technology needs.
CMOS milestones
Presenters at the 2001 IEDM revealed significant milestones in continuing conventional CMOS transistor technology (see "Smallest conventional CMOS devices yet" below) and advances in associated wafer-processing skills. However, a noticeably smaller audience of ~900, compared to 1700 in 1999 (Washington, DC) and 2300 in 2000 (San Francisco, CA), attended this key conference. According to IEDM general chair, MIT's Judy Hoyt, low attendance this year was due to travel budget cuts, but also current international sensitivity to traveling to the US capitol.
Many of those who did attend directed their attention to low-k and high-k materials issues associated with the relatively short-term continuation of CMOS technology.
Low-k technology
The continued development of copper low-k processing for advanced CMOS is focused on reliably applying ever softer "ultra-low" <2.3 dielectric constant materials:
- A large team of engineers at International Sematech, Austin, TX (including engineers from TI, Motorola, IBM, and others), is addressing the propensity of porous candidate materials not to maintain mechanical strength and adhesion through CMP processing and k <2.3 after integration. Work at International Sematech has also shown a degree of incompatibility with DUV photoresist, which is suspected due to etch and ash processing using nitrogen. The engineers have seen results with "one spin-on porous silica material" that maintains its ~2.3 k value after all processing.
- Engineers from TSMC, Hsinchu, Taiwan, and Sony, Tokyo, Japan, have separately succeeded in incorporating electropolishing as an alternative to CMP, thus allowing use of mechanically weaker low-k materials in four-level copper low-k interconnects. At TSMC, for example, this process has achieved production yields, compared to a process using conventional CMP, on 4Mb SRAMs.
- Other work at International Sematech (in conjunction with Infineon Technologies, Munich, Germany; Philips, Eindhoven, The Netherlands; and Novellus Systems, San Jose, CA), is investigating the interaction between porous low-k materials and CVD barriers, especially diffusion of CVD precursors into the pores of the low-k material and subsequent metal deposition inside the low-k material. While still needing more complete characterization, the International Sematech-based group has seen positive results with a novel 5nm-thick TiN(Si) copper barrier used with JSR KLD 5109 ultra-low-k material.
- Engineers at Hitachi, Tokyo, Japan, have developed the processing necessary to integrate Dow Chemical's SiLK ultra-low-k material with a SiCN barrier, overcoming high capacitance problems associated with using SiN.
High-k dielectric
Emphasizing the crucial importance to the future of CMOS for developing high-k and metal gate technologies, IEDM included two sessions on this timely topic. While development work continues with zirconium silicates and other alternatives such as lanthanide oxide (Pr2O3), Kwangju Institute of Science and Technology, Korea, and RuxTax films, North Carolina State University, a significant portion of the development activity here is building around hafnium oxide (HfO2):
- Motorola, Austin, TX, engineers have fabricated polysilicon-HfO2 gate stack MOSFETs, depositing HfO2 at 550µC with MOCVD and performing cosilicidation that produces an oxide at the polysilicon interface. This process has produced acceptable NMOS performance, but further work is needed to improve PMOS performance.
- Working with a variation to silicon surface nitridation ("bottom nitridation"), researchers at the University of Texas Microelectronics Research Center, Austin, TX, have incorporated nitrogen in the upper layer of HfO2 via sputtering, resulting in improved and even superior MOSFET characteristics.
- At International Sematech, in a comparison of self-aligned MOSFETs fabricated using atomic-layer-deposited ZrO2 or HfO2 as gate dielectrics and polysilicon as gate electrode, overall transistor characteristics were better for HfO2. Among the advantages were tolerance to a source-drain anneal cycle at 1000µC for 10 sec and mobility degradation of ~15%. Further process optimization is needed, however, to improve threshold voltage and drive current.
- A team of engineers from Yale University, Jet Process Corp., New Haven, CT, and IBM, Hopewell Junction, NY, have shown that adding aluminum (Al) to a HfO2 film substantially increases its crystallization temperature; the propensity of HfO2 to crystallize with subsequent processing temperatures leads to greater leakage. Specifically, 6.8% Al raises the temperature ~200µC and 31.7% raises it ~400µC.
The overall message at the 2001 IEDM was that Moore's Law definitely has life and that fabrication technologies and designs are emerging that will bring the industry to the projected 10nm MOSFET barrier. The beauty of IEDM is that it is also the industry meeting where root sources of eventual CMOS replacement technologies (see, for example, the figure on this page) and fabrication diversification for new products emerge (see "Unique fingerprint-detecting MEMS" above).
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Smallest conventional CMOS devices yet
CMOS watchers look annually to the IEDM for evidence on the viability or death of Moore's Law. This year's smallest conventional MOS devices were as follows:
- A 16nm planar NMOS room-temperature FET, with a nonoverlapping source-drain design, has been manufactured by engineers at STMicroelectronics, Crolles, France, using currently standard 130nm-node processing. Controllably patterning an 80nm polysilicon SiGe gate oxide stack is done by selectively etching the SiGe layer to sublithographic 16nm devices (see figure).
- In a late paper at IEDM, engineers from Advanced Micro Devices, Sunnyvale, CA, and Stanford University, Palo Alto, CA, revealed details of a 248nm lithography-patterned 15nm gate-length planar bulk-silicon CMOS transistor achieved mainly via aggressive scaling of the entire transistor. While this design will need the addition of high-k and metal gate technologies in the future, experimental work was done with a polysilicon and 8Å effective oxide thickness nitride-oxynitride gate stack.
These accomplishments are clearly five times smaller than currently fabricated devices representing three to four device generations in the future, evidence that Moore's Law was not declared dead at the 2001 IEDM.
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Unique fingerprint-detecting MEMS
Engineers for various laboratories at Japan's NTT presented a new MEMS fingerprint sensor at the 2001 IEDM. It has potential for widespread use, particularly in the fields of personal identification and security. Each of the sensor's 50µm pixels has a thin film "sensitivity plane" and a sensing circuit below. Fingerprint ridges characteristically deflect pixels (fingerprint valleys do not deflect adjacent pixels) creating a capacitance change in the sensors. This MEMS is fabricated with CMOS technology. It works with wet or dry fingers and also shows sufficient mechanical strength against finger pressure.
Pieter "Pete" Burggraaf has more than 25 years of experience in the semiconductor industry, including work at Motorola, Siemens, and ASM. He can be reached at 875 S. Yucca Dr., Wickenburg, AZ 85390; ph 928/684-1265, fax 928/441-3139, [email protected].