Minifab key to low-cost chip production*
02/01/2002
We have a concrete plan for a new kind of semiconductor fab that can efficiently produce small runs of many different types of system chips. With this new agile minifab approach, a chipmaker could turn a profit with a facilities investment of only $83 million (¥10 billion), a tenth the $830 million (¥100 billion) investment now required to build sufficient conventional fab capacity to break even. The agile minifab would drastically cut both production cost and turnaround time for low-volume system chips, and allow flexible response to changes in the market as well.
Excess supply will continue to drive down prices and send the chip industry into cyclical dives as long as the only way producers can reduce costs is by ramping up production volume. Conventional megafabs cannot adjust to changes in the market. When demand falls off, they just start piling up inventory. Like the hulking ships in the Spanish armada, or the supposedly unsinkable giant Japanese battleship Yamato, semiconductor fabs have become too big to maneuver.
As the electronics industry faces ever shorter product life cycles, suppliers must find ways to produce smaller runs of chips more cheaply and more quickly, flexibly changing product mix as needed and adjusting production to market demand. The wafer fab of the future must be an agile fab.
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Our agile minifab model has capacity of 100 lots/month and efficient control software that can allocate lots in close to real time. To reduce time wasted in preparation, transport, and waiting, minifab tools will need to do single-wafer or small lot processing instead of batch processing. The tools should each run multiple processes, which means they will need cleaning technology within the process chamber. To bring down the cost of multiple layers, the minifab will use low-cost coating for interlayer dielectrics instead of CVD, and low-cost plating for copper instead of sputtered aluminum. Ideally, the minifab will use direct-write systems to reduce mask costs, but since patterning a 200mm wafer with an e-beam writer now takes 2-3 hours, that will have to be improved 20- to 30-fold over the next several years before it is practical for production. We are using conventional lithography and masks for now.
Also key to the agile minifab, besides these low-cost, low-volume tools, is the software to adjust production almost instantly. Since the minifab has only a tenth the work in process at any one time, it can simulate lot management in close to real time, adjusting lot starts to get the fastest turnaround time or the highest output. With wafer starts of around 50 lots, a standard computer can run a simulation in about one minute.
The megafab has ten times as many tools and ten times as many lot starts, making the system too complex to run any usefully precise simulation in any practical amount of time. But the minifab makes close to real-time simulation possible, so lot allocation can be changed in real time, consistently maintaining the best number of starts, and greatly improving turnaround time. Production can be immediately reallocated when problems occur, when maintenance is scheduled, or when the product mix changes.
The minifab will also be a tenth the size of the megafab, requiring only a tenth the cleanroom area. With total transport distance within the fab reduced to only a few meters, compared to 100 meters or more in a megafab, no high-speed transport system is needed. Our simulation suggests that for this fab 0.3 people and basic supporting tools should suffice for loading, unloading, and transport.
The ability to allocate production in real time can also significantly reduce the need for investment in power and water supplies. While current energy budgets must make sure there is enough electricity available for the peak usage of each tool plus some additional margin, agile fab software can schedule equipment use so peak energy demands from one tool do not overlap those from another tool, evening out power usage at a much lower level. Our simulations suggest actual power usage for each lot can be kept to less than half the usual allotted electrical capacity, and water usage can be similarly leveled out, which would significantly reduce the cost of building a fab's supporting infrastructure. — Katsuya Okumura, Tokyo University; Kunihiro Mitsutake, Toshiba Semiconductor Process Technology Center
*This article was translated for Solid State Technology from the November 2001 issue of Nikkei Microdevices, our partner in Japan.
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Ohmi heads new Japanese research consortia*
Tadahiro Ohmi, Tohoku University heads two new Japanese research projects. Other ongoing Japanese research consortia include the government-supported MIRAI project on basic 0.07-0.05µm technology, and the privately funded ASKA/Selete efforts in 0.10-0.07 production processes.
The new HALCA project led by Ohmi aims to develop efficient mass production technology for making low-volume runs of specialized system chips. HALCA, which stands for High-Performance and Agilent Cleanroom Association, will get $54 million (¥6.5 billion) over three years, $33 million from the government, and $21 million from industry.
The Japanese government allotted $6.6 million (¥790 million) in September to see the project through March. Companies participating are Ulvac, Ebara, Sharp, Seiko Epson, Sony, Dainippon Screen, Tokyo Electron, Toshiba, Rohm, and Sanyo. HALCA will join the ASKA and MIRAI projects in the new government-funded cleanroom at Tsukuba University scheduled to open in April, using half the 1500 m2 originally allotted to MIRAI.
HALCA aims to reduce energy use on its LSI production line 60% by 2003. Since current fabs are optimized for high-volume production, significant amounts of energy, gases, and other materials are wasted when many different small lots are made. So the project will develop more efficient production tools for low volumes. It specifically aims to improve furnaces and tools for CVD, cleaning, implantation, and etching, and to build a demonstration line. The technology is based on the ideas for the agile fab developed by Toshiba Semiconductor's Katsuya Okumura, now at Tokyo University.
While HALCA focuses on making improvements to existing equipment that can be done in a year or so, the new DIIN project (New Intelligence for IC Differentiation — initials are read backwards) headed by Ohmi aims to develop revolutionary technology and technology for which Japan will own the rights. Ohmi wants to develop all low-temperature processes, below 500µC, which can also be used for flat panel displays. In addition, the project seeks to use a process flow synthesizer; direct write exposure; single-chamber, multiprocess tools; and five-wafer lots. Besides process technology, it also aims to rethink design technology so total time from design to finished production of a system chip can be reduced from 400 to 12.5 days.
More than 50 companies are participating, including Sharp, Seiko Epson, Rohm, Tokyo Electron, and Advantest. Budget for the six-year project is $104 million (¥12.5 billion). Some $35 million of that went to build a new cleanroom laboratory at Tohoku University, completed in November. — Masahide Kimura, editor, Nikkei Microdevices
*This article was translated for Solid State Technology from the October 2001 issue of Nikkei Microdevices, our partner in Japan.