Competitive success through accelerated yield learning
02/01/2002
Ken Schroeder, KLA-Tencor
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Although the semiconductor industry is currently experiencing one of the worst downturns in its history, the one thing we know for sure is that this too shall pass. And when it does, IC manufacturers must be ready to respond to rapidly escalating demand for the leading-edge chips that will power our electronic future. If the cycles of the past have taught us anything, it's that true leaders in this industry don't just weather the storm — they strategically invest their way out of the downturn so that they can reap greater rewards when the inevitable upturn arrives. Today's top chipmakers are doing just that. It's evident in the continued strong capital spending of IDMs like Intel, and in the aggressive expansion plans of foundries like TSMC, with its $20 billion, 10-year plan. But it's not just spending that matters. What counts are the strategic investments that will ensure future success.
Historically, the majority of strategic investments have been in core process or material advances. But given today's accelerating technology life cycles, spending in areas that can speed production success, such as process control, has become equally critical. Savvy chipmakers recognize the investment for what it is: a true profit center. The reason is simple: it holds the key to ensuring that those leading the charge on next-generation device technologies can fully capitalize on both the optimum window of market opportunity and peak selling prices for their advanced devices.
Why is process control so important? One of its fundamental value propositions is that it helps to accelerate yield learning by detecting, sourcing, and fixing process problems. The faster a manufacturer completes this cycle, the faster it can get products to market in volume. Considering it took 23 years for the ubiquitous television to reach the first 10 million customers and less than 18 months for the latest video-gaming machines to achieve the same number of customers, it's clear that the speed at which the marketplace adopts new technologies continues to accelerate. Yet the only way to get to market faster is to accelerate the successful production ramp of next-generation technologies. That's what process control is all about.
Many of today's leading chipmakers have already figured out that the revenue and profit potential derived from this fundamental value proposition can be staggering. Even shortening the typical development time from 12 to 9 months could represent millions of dollars in increased revenue due to higher average selling prices (ASPs) for devices. One can further hypothesize about the revenue potential of reducing the production ramp by another couple of months or increasing yield by 10%. The bottom line is that by accelerating time-to-yield, you can speed time-to-market and maximize your fab return on investment (ROI).
While it's evident that accelerated yield learning is essential to a fab's success, the challenges inherent in any yield optimization program are now being exacerbated by the unprecedented convergence of three major technology transitions: copper, sub-130nm design rules, and 300mm wafers. Each of these poses major yield-learning challenges. Sub-wavelength lithography requires more complex reticles, which in turn increase the impact of the mask error enhancement factor, ultimately resulting in significantly smaller lithography process windows. Incorporating copper means grappling with dual damascene architectures, copper CMP, and sub-surface defects such as copper voids. Finally, in 300mm processing, the primary hurdle is maintaining process uniformity across these larger-diameter substrates.
Taken together, these new technologies are creating formidable challenges, including the ability to detect both new types of yield-killing defects and smaller yield-killing defects within an expanding critical area. Currently, an electrical defect density of < 0.1 defects/cm2 is required to achieve acceptable yields at the 100nm node. Essentially, that equates to only one defective contact/3.6 billion vias and only three defects for every 5 km of metal in advanced logic or microprocessor chips. The needle shrinks while the haystack grows.
Achieving and maintaining this stringent defect density necessitates the capture, analysis, and understanding of virtually every physical defect type in the process line. Yet to find the defects that matter, you must increase inspection sensitivity, which means sorting through thousands of detected physical and nonrelevant defects to isolate the few dozens of electrical defects that will impact yield. Being able to do this quickly is the key to accelerated yield learning, but it requires new approaches to process control.
Current yield-learning strategies that use either long loop or short loop methodologies have several disadvantages when applied to advanced semiconductor manufacturing. The memory long loop method provides approximate electrical defect location, but it requires significant de-processing to isolate yield-limiting defects to a specific layer. Also, it requires failure analysis that could take several weeks, limiting its effectiveness for rapid yield learning, especially in the more cost- and time-sensitive development phase.
The short loop method, while significantly faster, is rarely representative of the real production process, leaving the door open for missing systematic defects. Chipmakers are forced to compromise on either speed or accuracy, leaving many weeks of material at risk, consuming enormous engineering resources, or creating the potential for a dangerous "yield bust" at final probe. While these yield-learning methodologies may have been adequate for earlier device generations, they will no longer be enough to support future technology innovation and the accompanying stringent process control requirements.
Revolutionary new defect inspection strategies are being developed to satisfy the simultaneous demand for speed, accuracy, and cost-effectiveness, while continuing to enable chip manufacturers to achieve their near-zero-tolerant process windows and accelerated yield-learning cycles. KLA-Tencor, for example, recently introduced a yield-learning methodology that uses customized test chips with in-line scanning electron beam inspection and voltage contrast technologies.
This new approach brings electrical test to frontend semiconductor processing to enable fabs to accurately, quickly target only those defects that will have the greatest impact on yield, without waiting weeks or months to obtain results from end-of-line electrical test. Thus, each yield-learning cycle can be reduced to a matter of just days.
As the industry hurtles toward the sub-100nm node, new approaches such as these will be needed so global chipmakers can harness the power of process control to increase their competitive edge and fab ROI.
Ken Schroeder is president and CEO of KLA-Tencor, 160 Rio Robles, San Jose, CA 95134; ph 408/875-3000, e-mail [email protected].
This article was adapted from the author's keynote address at the 2001 International Symposium on Semiconductor Manufacturing (ISSM).