Implant and process challenges on the ITRS front-end process roadmap
01/01/2002
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SPECIAL REPORT: 2001 ITRS
Ion Implantation
Larry Larson, Howard Huff, International Sematech, Austin, Texas
Solid State Technology has been working with the leaders of various technical working groups of the 2001 International Technology Roadmap for Semiconductors (ITRS) to outline highlights and crucial changes in the new ITRS for a broad range of fab operations, beginning here with front-end processing and continuing through wafer-level test. For an overview of the roadmap by its chairman Paolo Gargini (Intel) and co-chairman Robert Doering (Texas Instruments), see p. 72.
Several key changes in front-end processing (FEP) requirements for the 2001 ITRS (see table; also see "Reading the 2001 ITRS tables" on p. 33) have been precipitated by a more complete effort to model the transistor. This effort was driven by the process integration and device structures (PIDS) TWG's adoption of a "share the pain" approach. Our approach models integration choices to accommodate accelerating technology requirements, which are balanced against available materials choices.
The "grand challenge" facing FEP at and beyond the 65nm-technology node lies in fabricating the basic transistor structure. This entails the development of a higher-k gate dielectric and the associated processing of the gate stack, as well as integrating the gate stack with a highly doped ultrashallow junction contacting the device.
A 65nm-node high-performance microprocessor (MPU) will require an equivalent oxide thickness (EOT) of 0.6-1.1nm and an extension junction depth of ~14nm. Beyond the 65nm node, both conventionally fabricated gate dielectric and the associated ultrashallow junction technologies reach significant technical barriers.
More specifically, near-term challenges facing implant-doping technology include the extension of conventional methods used to fabricate ultrashallow junctions into the sub-65nm regime, simultaneously achieving the required depth of the scaled drain extension junction and high lateral abruptness in a manufacturable process.
There are several key requirements associated with ion implant dopant introduction, control, and related processes:
- Doping and activation processes will have to achieve shallow source-drain junctions having parasitic resistance <16-20% of the ideal channel resistance;
- Parasitic capacitance needs to be controlled to achieve <19-27% of the gate capacitance, consistent with acceptable drive current and minimum short-channel effect;
- Activated dopant concentration must be greater than solid solubility in dual-doped polysilicon gate electrodes (p+ polysilicon doping with an active concentration of ~2x1020/cm3 is required.);
- Processing must form continuous self-aligned silicide contacts over shallow source-drains; and
- Metrology must provide 2-D dopant profiling of ultrashallow junctions.
Challenges in making contact to ultrashallow device junctions include the placement of halo dopant implants with the necessary precision and activation technology to eventually achieve ~14nm ultrashallow junction depths with a sheet resistance of ~760W/sq with high depth and lateral abruptness, similar to a perfect square profile junction at the dopant's solid solubility. Materials effects that must be accommodated include nonequilibrium dopant incorporation and metastable dopant stabilization.
The combination of ion implantation and anneal is expected to be the dominant process solution into the second half of this decade. More advanced annealing techniques, such as laser thermal and microwave annealing, are also being evaluated and assessed for their potential utilization. Deposited layers, however, may be the ultimate ultrashallow junction replacement technology during the next decade.
New materials will also add challenges to methods used to dope and activate silicon. For example, in addition to the scaling-imposed need for producing ultrashallow, highly activated junctions, the limited thermal stability of a number of proposed high-k materials will place limits on thermal budgets associated with typical junction-annealing cycles for dopant activation. Significant process, manufacturing, and integration challenges are associated with the higher-k gate stack module. On the other hand, this concern is driving the fabrication of more thermally tolerant and, perhaps, more complex high-k material combinations consistent with conventional planar CMOS processes.
Other FEP issues
Effective increase in gate dielectric thickness associated with polysilicon depletion and channel autodoping associated with boron out-diffusion from a p+ polysilicon gate will eventually require phase-out of conventional dual-doped polysilicon gate electrode material. The current model for poly-doping requirements is based on a 25% allotment of the allowable poly depletion layer in relation to EOT. This will result in less than optimal transistor performance and suggests that metal gates will probably be needed in the near future. But metal gates are unlikely to be ready for manufacturing before 2007. The industry needs to work on developing enhanced means of activating doped polysilicon for minimizing depletion and achieving tighter control of the work function.
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The maintenance of acceptable off-state leakage with continually decreasing channel lengths will require that channel-doping levels increase to offset degradation in short-channel effects for extremely small devices. Although both vertical and lateral channel engineering can minimize degradation from these effects, it will not be possible to scale threshold voltage without a large increase in off-state leakage. From the "share the pain" approach, these scaling problems have been made more difficult through a less aggressive plan for scaling the gate dielectric — a direct result of the unavailability of a sub-1nm higher-k gate dielectric material meeting the required device metrics, in particular, mobility. This places even greater demands on channel-doping engineering to optimize device performance.
Typically, lateral channel engineering, an effective method to improve device performance, is accomplished by angled implants following gate patterning, thus increasing dopant concentrations near the active drain extension. The resulting channel profile is device-size dependent. Smaller devices have higher average channel-doping levels. This can be used to tailor the relationship between threshold voltage and device size to improve device performance.
For lateral channel engineering to be effective, the lateral profile must vary over the length of the channel. This will become extremely difficult as channel lengths are continually reduced. Diffusion effects degrade profile abruptness, making the scaling of vertical and lateral channel profiles extremely difficult. These profiles must be very localized to maximize their beneficial effect on device performance.
The management of short-channel effects will have a significant impact on processes used for doping drain extensions, channels, and channel edges. Drain extension doping levels will increase, driven by the need to reduce junction depth while minimizing parasitic resistance. Similarly, drain extension doping profiles, which in earlier technologies required lateral grading for minimizing hot carrier damage, are becoming more laterally abrupt. This has been made possible by reduction in VDD.
The complexion of the abruptness need depends on device type. For p-channel (PMOS) devices, sensitivity simulations indicate that above a critical abruptness value, only a marginal reduction in parasitic resistance is achieved and narrow gate length devices are harder to build. Improving abruptness beyond some critical value shows only minor improvements. Yet PMOS devices are critical, challenged by continued device shrinks due to their already small mobility compared to NMOS devices. For n-channel (NMOS) devices, a more abrupt source extension junction leads to a higher source injection velocity and higher resulting drive current. For NMOS, higher abruptness values are desirable, although not as significant as the desired improvements in PMOS.
Transistor structure
Beyond the 65nm node, the grand challenge is simply stated as "transistor structure"; selecting a higher-k gate dielectric material will not in itself solve the future's multiple gate stack issues.
The PIDS chapter of the ITRS outlines several truly innovative alternative solutions currently being explored. For example, raised source-drain structures may provide some relief from ultrashallow junction, abruptness, and contact-resistivity issues. Nonclassical MOSFET structures, including double gate structures on SOI, vertical transistor structures, or perhaps the ballistic transistor, may be useful candidates. Longer-range solutions involving electron spin devices and utilization of single-electron transistors are just a few potential candidates, although their future appears more than 20 years away, at best.
Larry Larson is co-chair of the ITRS doping sub-TWG for the FEP TWG and associate director and ultrashallow junctions program manager for the FEP Division at International Sematech, 2706 Montopolis Dr., Austin, TX 78741; ph 512/356-7145.
Howard Huff is chair of the ITRS starting materials sub-TWG, co-chair of the thermal/thin films sub-TWG for the FEP TWG, and senior fellow and materials science program manager at International Sematech.
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Reading the 2001 ITRS tables
The colored boxes in the 2001 ITRS tables on pp. 33-52 should be interpreted as follows: white boxes = "solution exists"; yellow boxes = "solution being pursued"; and red boxes = "no known solution."
Solid State Technology's versions of the tables are greatly truncated in time; while there are seven technology nodes in the complete tables, we present only today's node and the ITRS-defined "short-term" and "long-term" horizons — seven and fifteen years out. These are accurately represented, but the truncated time frame may under- (or over-) emphasize the emergence of "no known solution" boxes.
The complete 2001 ITRS and tables are available for viewing and printing as electronic documents at http://public.itrs.net.