The end of optical on the ITRS lithography roadmap
01/01/2002
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Harry Levinson, Advanced Micro Devices Inc., Sunnyvale, California
The smaller features and tighter tolerances in the 2001 ITRS deliver the message that the industry is clearly approaching the physical limits of optical lithography (Table 1). Without some invention that significantly changes the way optical lithography is practiced, a next-generation lithography (NGL) technology — such as extreme ultraviolet (EUV) lithography or electron projection lithography (EPL) — will be required to extend the roadmap to the 45nm node and beyond. (Even proposed NGL technologies at the 22nm node may not provide adequate capability, at least without significant further invention.)
 Developed for volume production, the AT:1100 is a dual-stage ArF lithography system for 300mm wafer processing with 100nm resolution. (Photo courtesy of ASML) |
Accordingly, NGL mask tables have now been included in the ITRS (Table 2). Other requirements, such as sensitivities and thickness requirements for resists, have been updated to be consistent with current visions of lithography's future. For example, the lower bound for resist sensitivity for EUV and EPL lithography has been reduced from 5mJ/cm2 to 2mJ/cm2, in response to concern over exposure tool throughput. This requires consideration of other parameters such as line-edge roughness, however, that could be worse at low doses.
As more is learned about NGL technologies, existing requirements will be refined, while additional requirements may be added; the current lithography chapter of the ITRS is far from the last word.
Still, optical lithography
At the same time, optical lithography is currently far from dead, and it will need to be extended further as NGL technologies are developed. This involves transitions to shorter wavelengths that bring new requirements in tools, masks, and materials. For example, lithography at 157nm will require exposure systems purged of oxygen and water, down to ppm. New grades of fused silica, transparent at 157nm, will be needed for photomask substrates, and new attenuating materials must be developed. Photoresists based on new chemical platforms are required for 193nm and 157nm lithographies.
As optical lithography approaches physical limits, key elements of the lithography infrastructure will be severely challenged. The mask error factor (MEF) becomes large for optical lithography practiced near the resolution limit. For example, a mask error factor of 3.5 is assumed for 65nm-node contacts. As a consequence, maintaining tight linewidth control will require exceptionally good photomasks. The transition to NGL may relieve the burden of large MEF, but this problem will be replaced by the need to generate an infrastructure to support radically new mask formats with their own challenges.
Because of maskmaking challenges, whether the masks are optical or NGL, maskless lithography is being contemplated as a potential solution for future nodes. This is being considered even though maskless technologies have well-known challenges that must be addressed to meet the throughput requirements for cost-effective manufacturing. Direct writing tools currently have throughputs of only a few wafers/hour. Since the throughput of direct writing tools will decrease with smaller feature sizes — all else remaining equal — technical advances are required just to maintain this level of throughput for future nodes. Further advances are needed to meet the throughput requirements of manufacturing. Regardless of the technology, optical or NGL, solutions will necessarily be complex and therefore expensive.
Cost reduction, process control
The transition to 300mm wafers provides less cost reduction for lithography than for many other semiconductor-manufacturing processes because wafer throughput of step-and-scan exposure tools is dependent on wafer size. Larger wafers will reduce scanner throughput or require significant increases in tool costs.
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Cost control and return on investment have again been recognized in the 2001 ITRS as among the difficult challenges for lithography. Among the economic issues are: achieving a constant or improved ratio of tool cost to throughput over time as we migrate to 300mm wafers, new exposure wavelengths, and NGL; developing affordable masks, both optical and NGL, particularly as required for the ASIC market; and achieving returns on investment for all segments of the industry (chipmakers, equipment and material suppliers, and infrastructure) with sufficient lifetimes for the technologies, especially single-node solutions at 90nm and below.
A viable semiconductor industry requires that all sectors — chipmakers, mask shops, equipment and materials suppliers — achieve returns on investment that enables them to be profitable and to make the investments in R&D necessary for continuing progress.
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Process control requirements challenge nearly all aspects of lithography, notably overlay, gate linewidth control for microprocessors, and low defect processing. Today's microprocessor gates after etch are <70nm long. This represents a nine-year acceleration relative to the 1994 roadmap. Such an acceleration necessarily makes it a challenge to meet current and future needs.
Controlling gate linewidths to ±10% of target size will necessitate exceptional masks, very low aberration exposure tools, superb metrology, and adequate process margin and low line-edge roughness (LER)resists. LER, added to the 2001 ITRS, is more important because molecular-level feature-edge roughness becomes significant in magnitude relative to permitted linewidth tolerances.
Overlay requirements are becoming tight, necessitating accurate alignment systems and measurement tools with reduced process sensitivities. Defect detection and prevention will be uniquely challenged; the very distinction between a defect and a legitimate feature will need to be understood.
Harry Levinson is ITRS chairman of the US lithography TWG and manager of strategic lithography at AMD Inc., One AMD Place, MS78, Sunnyvale, CA 94088; ph 408/749-2558.