A high-level view: The 2001 ITRS from altitude
01/01/2002
Paulo A. Gargini, Intel Corp.
Robert R. Doering, Texas Instruments Inc.
The 2001 International Technology Roadmap for Semiconductors (ITRS) reflects two overall messages: the entrenchment of international consensus building and yet tighter periods between industry technology nodes.
The participation of more than 800 experts from Europe, Japan, Korea, Taiwan, and the US ensures the 2001 ITRS' 15-year outlook is a valid source of guidance for the worldwide semiconductor industry. We have seen this document evolve from a "national" publication through 1997, coordinated by the Semiconductor Industry Association (SIA), to its present form. Participation is now fully supported by the SIA, the European Electronics Component Manufacturers Association, the Korea Semiconductor Industry Association, the Japan Electronics and Information Technology Industries Association, and the Taiwan Semiconductor Industry Association. This cooperation has existed since the 1998 ITRS update, but was even more evident to us with the development of the 2001 ITRS.
The process of producing the ITRS, which is updated in even years and republished in odd years, provides a true forum for international discussion, cooperation, and agreement among leading semiconductor manufacturers and equipment, materials, and software suppliers. Equally important, it involves researchers from universities, consortia, and government labs.
The benefit to the industry is that starting with this document as a common reference and through cooperative efforts among various ITRS participants, the challenge of R&D investments will be cooperatively and more uniformly shared by the whole industry. At the same time, fundamental elements that foster innovation will continue to be valued and cultivated by individual companies.
The most significant changes between the 1999 and 2001 ITRS editions are in minimum feature sizes. In particular, lithography half-pitch and transistor gate-length strongly influence most other parameters in the ITRS, and their scaling trends have continued to accelerate.
As measured by DRAM half-pitch, the 1999 ITRS targeted technology nodes of 130nm in 2002, 100nm in 2005, and out to 35nm in 2014. The 2001 ITRS indicates that we have already reached 130nm, one year early, and should reach 100nm in 2003, two years ahead of the 1999 ITRS projection. Furthermore, the new ITRS has adopted a more precise 0.7x scaling that rounds future nodes to 90nm in 2004, 65nm in 2007, 45nm in 2010, 32nm in 2013, and 22nm in 2016.
In addition, the overall node acceleration between the 1999 and 2001 roadmaps is two years asymptotically. In contrast, the scaling of the smallest feature size in ICs — microprocessor (MPU) transistor-gate lengths — is almost six years asymptotically. For example, a 25nm gate length is now projected for 2007 compared to ~2013 in the 1999 ITRS. This is in part due to the recent trend of purposely reducing gate lengths below the directly printed size by a variety of post-lithographic processes. The 2001 ITRS now distinguishes "physical" gate length from gate length "printed in resist." For example, where the 1999 roadmap showed a gate length of 65nm in 2005, the 2001 roadmap has 45nm printed and 32nm physical gate lengths in 2005.
At the new 2016 "long-term" horizon of the 2001 ITRS, the physical gate length is projected to be a mere 9nm, essentially equivalent to the most optimistic current projections on the extendibility of MOS transistors and the smallest experimental MOSFETs ever built — an 8nm gate-length. These experimental devices used a special source-drain structure that has not yet been demonstrated to be practical for high-performance ICs.
The new 2001 ITRS is now entering a phase where it is necessary to begin considering "beyond planar" or even "post-CMOS" devices. Here, the 2001 ITRS includes discussions on emerging technologies, focusing on research status assessments and pointing out opportunities for future R&D on principal barriers to practical implementation.
But most of the 2001 roadmap continues to be devoted to details associated with scaling to "ultimate CMOS." For example, the aforementioned acceleration of transistor gate lengths has resulted in earlier requirements for thin gate dielectrics and shallow source-drain junctions. The 1999 ITRS had equivalent gate oxide thickness of 1.5-1.9nm in 2002, 1.0-1.5nm in 2005, and 0.8-1.2nm in 2008. The 2001 ITRS projects equivalent thickness of 1.2-1.5nm in 2002, 0.8-1.3nm in 2005, and 0.6-1.1nm in 2007. The "red box" in the roadmap table for this parameter begins in 2005, pending the development of a satisfactory high-k dielectric or other solution.
Similarly, junction depths for drain extensions were 25-43nm in 2002, 20-33nm in 2005, and 16-26nm in 2008 in the 1999 ITRS. These have been reduced to 22-36nm in 2002, 13-22nm in 2005, and 10-17nm in 2007.
Despite aggressive scaling in the 2001 Roadmap, not all process and material parameters have been further squeezed. Notably, the scaling of interlevel metal dielectric constants has actually moderated. In 1999, it was envisioned that this parameter would be 2.7-3.5 in 2002, 1.6-2.2 in 2005, and <1.5 in 2008. The 2001 ITRS actually indicates larger values in 2005 and beyond, enabled in part by design solutions, such as better use of metal layers in hierarchical fashion.
Overall, the 2001 ITRS depicts a more selective approach to scaling. ITRS participants have agreed that scaling of parameters that really control and improve product performance has accelerated, demanding a maximum research effort. Conversely, other parameters do not need to be accelerated as much as was suggested by the 1999 ITRS.
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Paolo A. Gargini is chairman of the ITRS and a fellow at Intel Corp., 2220 Mission College Blvd., Santa Clara, CA 95052; ph 408/765-9646, e-mail [email protected].
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Robert R. Doering is vice chairman of the ITRS for the US and a senior fellow at Texas Instruments Inc., 13588 North Central Expwy., MS 3730, Dallas, TX 75243; ph 972/995-2405, e-mail [email protected].