The challenges in the ITRS interconnect roadmap
01/01/2002
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Christopher Case, BOC Edwards, Murray Hill, New Jersey
The 2001 ITRS continues to reflect the hierarchical wiring design trend featuring reduced aspect ratios (as an alternative means of reducing capacitance) and less aggressive scaling of the dielectric (see the table). The latter change expands the development window to address the difficulty in integrating new low-k dielectrics into a damascene architecture and acknowledges benefits from the use of copper wiring. Managing this rapid rate of materials introduction and concomitant complexity represents the overall near-term challenge.
For the long term, material innovation with traditional scaling will no longer satisfy performance requirements. Near-term, difficult challenges for IC interconnect include rapid introduction and integration of new materials and processes necessary for new structures, achieving dimensional control, and maintaining physical and electrical reliability of interconnect structures. These challenges must be met while maintaining manufacturability and defect management targets that meet overall cost and performance requirements.
Manufacturability involves addressing plasma damage, contamination, thermal budgets, cleaning of high-aspect-ratio features, defect-tolerant processes, and elimination or reduction of control wafers. Acceptable reliability will only come through the control of interfaces, more emphasis on modeling, and the elimination of failure mechanisms.
To meet conductivity requirements and reduce dielectric permittivity, the rapid introduction of new low-k dielectrics, and chemical vapor deposition (CVD) conductor, barrier, and nucleation layers, as well as additional requirements for SOC (system-on-a-chip), create significant process and process integration challenges. Interfaces, contamination, adhesion, mechanical stability, electrical parametrics, and thermal budget — confounded by the increased number of wiring levels for interconnect, ground planes, and passive elements — create a difficult-to-manage complexity.
Although the technical product driver for the smallest feature size remains the dynamic memory, emerging SOCs are set to challenge and match microprocessors for increased complexity and tighter design rules.
The need for continually lowering insulator dielectric constant is now firmly on track. Fluorine-doped silicon dioxide (k = 3.7) combined with Cu was introduced at the 180nm technology node and insulating materials with k = 2.6-3.0 are being introduced for the 130nm node. A primary integration challenge with low-k materials is adhesion failure of barrier or capping materials with the dielectric during planarization. Porous low-k materials, a key focus area for planarization development efforts, are even more problematic and are a driver for new CMP processes.
Atomic layer deposition (ALD), characterized by excellent conformality and thickness control, is receiving attention for deposition of barriers and nucleation layers (as well as high-k dielectrics). Doped Cu has also emerged as a potential solution for improved Cu reliability, but this needs to be balanced against the increased Cu resistivity that occurs. Increases in Cu resistivity due to electron-scattering effects will become an important factor in the long term and are first expected to limit conductor performance at intermediate wiring levels around 2007. (Another potential conductor solution combines Cu electrochemical deposition and planarization to reduce feature overfill.)
Combinations of materials and associated processes create an array of process complexities to address. For example, increased integration challenges associated with etch, strip, and clean steps might require novel approaches, such as cleaning with dense fluid or supercritical CO2 combined with solvents and surfactants. Alternative hydrogen-reducing gas chemistries might be needed for stripping photoresist from porous silicon oxide or similar low-k materials. Promising hybrid approaches will combine multiple technologies in gas and liquid phases to meet both surface preparation, cleaning, and stripping requirements. Other issues that will affect the future development of these technologies include finding new chemistries that are compatible with ESH mandates, selectivity needs, and electrical requirements.
CMP remains the leading planarization technology in current and future manufacturing. But development will continue in alternative metal planarization techniques — chemically enhanced planarization (CEP) and spin-etch planarization (SEP). These two approaches use chemical or electrochemical removal of metals. The 2001 ITRS spells out new dishing-erosion-thinning metrics for CMP.
Three-dimensional process control of interconnect features, with its associated metrology, is necessary for IC performance and reliability. The multiplicity of levels combined with new materials, reduced feature size, and pattern-dependent processes create this challenge. Dimensional control is a key challenge for present and future interconnect technology generations. The dominant damascene architecture requires tight control of pattern transfer, etching, and planarization. To extract maximum performance, interconnect structures cannot tolerate variability in profiles without producing undesirable RC degradation. These dimensional control requirements place new demands on high-throughput imaging metrology for measurement of high-aspect-ratio structures.
Dimensional control will become even more critical as new materials, such as porous low-k dielectrics with weaker mechanical properties, play a role.
High-k materials and capacitor electrodes — which might contain compounds such as barium strontium titanate or metals including ruthenium — have their own unique set of challenges.
New interconnect concepts
The most promising near-term solution anticipated for the global interconnect problem is design modifications to minimize global wiring lengths. One option is to move some interconnects from the primary chip to thicker metallization with higher performance on the package or on a supplementary chip designed to carry only interconnects. These signals would then be transferred back to the primary chip. In some cases a "sea of leads" approach might be used to provide major density increases in I/O to benefit not only global interconnect, but at the same time power and ground connections.
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Long-term, material innovation with traditional scaling will no longer satisfy performance requirements. Delay associated with global wiring and the management of crosstalk and noise must be addressed with increased development activity. SOCs may alter the picture or technology timing because chip functionality can be traded for scaled density so that chip pricing is not driven predominantly by chip area.
A relatively radical alternative to the usual metal-dielectric interconnect option is to use electromagnetic transmission of signals from one part of a chip to another. This option takes the form of a "LAN on a chip" with transmitters and receivers combining antennas and appropriate signal generation and signal detection circuitry.
Optical interconnects are considered a primary option for replacing the conductor-dielectric system for global interconnects. The optical approach has many variants, the simplest perhaps having emitters off-chip and only free-space waveguides and detectors in top layers on-chip, with progressively more complex options culminating in complete monolithic emitters, waveguides, and detectors. Three-dimensional interconnects have been proposed as one of the most promising solutions to achieve high-density device packaging and interconnects.
There are several more radical options for global interconnect solutions that may offer unique advantages, including nanotubes, spin coupling, and molecular interconnects. Recent measurements have shown that nanotubes can have very high conductivity based on ballistic transport and can be grown at designated locations using specialized seed sites. The ability to connect nanotubes from site to site has also been demonstrated. Ultimately, interconnect innovation with optical, rf, or vertical integration combined with accelerated efforts in design and packaging will deliver the solution.
Christopher Case received his PhD in engineering at Brown University. He is chair of the ITRS interconnect working group and CTO at BOC Edwards, 100 Mountain Ave., Murray Hill, NJ 07974; ph 908/771-6409, e-mail [email protected].